JPH022164B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention is directed to multiple programmable time monitoring circuits.

<Background> Conventionally, this type of programmable time monitoring (hereinafter "time monitoring" will be abbreviated as "timer") circuit has been realized by a binary counter in which each circuit is constituted by a flip-flop. Therefore, when it is necessary to implement a large number of timer circuits in hardware, there is a drawback that the amount of hardware becomes enormous.

In addition, in conventional timer circuits, the update interval of each counter depends on an external reference clock (constant value), so in order to realize a timer circuit that can set a wide range of monitoring time values, it is necessary to increase the number of bits of the counter. It was necessary to increase.

<Summary of the Invention> In order to solve these drawbacks, the present invention unifies the timer control circuit, enables dynamic allocation of timer counters, and increases the number of timer circuits that can be set with a small amount of hardware. By setting a reference timer value at the time, a timer circuit is realized that allows a wide range of timer settings with a small number of counter bits.

<Embodiment> Figure 1 is an example of the format of a timer control word (sometimes written as TMCW) used in an embodiment of the present invention and output from an external circuit. Monitoring time value field, 8th and 9th
2-bit reference timer value field,
10, 2-bit timer type field of the 11th bit, 4-bit pass number group identifier field of the 12th to 15th bits, and 8 of the 16th to 23rd bits.
The monitoring time value field, which consists of a bit pass number field, can be set to a value between 0 and 255, and when the set value is multiplied by the reference timer value described below,
The required monitoring time is reached. In the reference timer value field, 10 milliseconds, 1 second, and 1 minute can be specified as the reference timer value. For example, if 1 millisecond is specified in the reference timer value field, if 1 minute is specified for 0 to 2560 milliseconds, it becomes possible to instruct monitoring of 0 to 256 minutes. The timer type field allows designation of T0 to T3, and up to four different timers can be set on the same line. The path number group identifier field indicates the timer request source, and can correspond to, for example, a processing routine within a communication control program. The path number field indicates the line number for which a timer is requested.

FIG. 2 shows a block diagram of an embodiment of the invention. 1 is a timer registration register unit that holds a timer control word output from an external circuit, 2 is a timer registration update control unit, 3 is a timer control word storage unit that holds a plurality of timer control words, and 4 is a timer registration register unit. This is a registered address pointer section that holds a timer control word storage section address, and has an incrementer/decrementer. 5 is an internal interval timer section having three types of reference value timer circuits specified by the reference timer value field of the timer control word; 6 is an update address pointer section that holds the timer control word storage address for timer update; It has data. 7 is the timer control word storage unit 3 when updating the timer.
This is a timer update register that holds the readout output of , and has a decrementer in its monitoring time value field. A comparator 8 compares the contents of the registered address pointer section 4 and the updated address pointer section 6.

An example of operation is shown next. When the timer control word is output to the timer registration register section 1, the registration update control section 2
is held within its control unit 2. The timer stack overflow flag indicating that the timer control word storage unit 3 has overflowed is checked, and if the flag is “0”, the value obtained by incrementing (+1) the registered address pointer unit 4 is used as the address to store the timer control word. Register to storage unit 3 Register unit 1
Stores the timer control word.

If an overflow occurs as a result of incrementing the registered address pointer section 4, that is, if the timer control word storage section 3 is full, the registered address pointer section 4 is updated and the timer control word storage section 3 is incremented. The timer stack overflow flag is set to "1" without being stored, and a timer stack overflow interrupt is generated to the external circuit. The external circuit can recover the overflowed timer control word from the timer registration register section 1.

When a timeout occurs from one of the timers in the internal interval timer section 5, the registration update control section 2
reads the timer control word from the timer control word storage section 3 using the contents of the update address pointer section 6 as an address, and stores it in the timer update register 7. Next, the reference timer value of the reference timer circuit that generated the interrupt is compared with the reference timer value specified in the reference timer value field in the timer control word of update register 7, and if they match, the monitoring time value of that timer control word is compared. Decrements the contents of the field. If the result of the decrement becomes "0", an interrupt is issued to the external circuit to generate a timeout. The external circuitry can retrieve the timed-out timer control word from the timer update register 7. If the result of decrementing the monitoring time value field is not "0", the timer control word is updated to the timer control word storage section 3 indicated by the update address pointer section 6.
Store it in If the reference timer values do not match, the update address pointer section 6 is incremented and the process moves to update the next timer control word.

When a timeout occurs in the timer control word, for example, TMCW(2) (FIG. 3) due to updating of the timer control word, the timer control word is deleted from the timer control word storage section 3. 3 is switched from the update address pointer section 6 side to the registered address pointer section 4 side, the contents of the timer control word storage section 3 at that time, that is, the timer control word TMCW (j+1), are read out, and this is stored in the timer update register. 7, the contents of the registered address pointer section 4 are decremented from FE to FD, the read address of the timer control word storage section 3 is moved to the update address pointer section 6 side, and the contents of the pointer section 6 are set to 02. The timer control word TMCW (j+1) in the update register 7 is updated, that is, TMCW (j+1) is written to address 02. In FIG. 3, TMCW (j+1) is the latest timer control word, and "-" indicates an empty area.

The update address pointer section 6 is sequentially incremented to update the timer control word, and when the update processing of the timer control word of the address where the contents of the update address pointer section 6 and the registered address pointer section 4 match in the comparator 8 is completed. , the update process due to the interruption of one reference timer is completed.

If the timer stack overflow flag is "1" and a certain amount of empty space is generated in the timer control word storage unit 3 due to timeout processing during timer update processing, the registration update control unit 2 will handle the timer stack overflow. After setting the flag to "0", an interrupt is generated to the external circuit to release the timer stack overflow. The external circuit can use this as an opportunity to output the timer control word held. It is desirable that the number of empty areas for generating timer stack overflow release interrupts be set to a plurality of values or more so that timer stack overflow generation and release interrupts do not occur alternately.

When a timer control word is received from an external circuit during timer update processing due to a reference timer interrupt, the registration update control unit 2 reserves the timer control word in the timer registration register unit 1 and updates the j-th timer control word. After the processing is completed, the update processing is interrupted immediately before proceeding to the update processing of the j+1th timer control word,
Performs registration processing of pending timer control words.

<Effects> As described above, the present invention can provide a large number of timer circuits with high accuracy and a wide settable range at low cost, and thus can be useful for improving the processing ability and cost performance of the device.

[Brief explanation of drawings]

FIG. 1 is a diagram showing an example of the format of a timer control word used in this invention, FIG. 2 is a block diagram showing an embodiment of this invention, and FIG. 3 is a diagram showing a timer control word when the timer control word times out. It is a transition diagram of the contents of the storage section and the contents of the registration and update address pointer section. 1: Timer registration register section, 2: Registration update control section, 3: Timer control word storage section, 4: Registered address pointer section, 5: Internal interval timer section,
6: Update address pointer section, 7: Timer update register, 8: Comparator.

Claims (1)

[Scope of Claims] 1. A timer registration register section that holds a timer control word consisting of a reference timer value, a timer type, a monitoring time value, a path number, and a group identifier to which the path number belongs; and a timer registration register section that stores a plurality of the timer control words. a timer control word storage section for reading a timer control word to be updated from the timer control word storage section; a registration address pointer section holding an address for storing a timer control word in the timer control word storage section; an update address pointer section that holds the address for output, an internal interval timer section that generates an interrupt signal every time the reference timer value indicated by the timer control word; means for storing the timer control word in the timer control word storage section indicated by an address obtained by adding 1 to the contents of the registered address pointer section; and an interrupt signal from the internal interval timer section, the update address pointer section addressed by
subtracting a certain value from the monitoring time value of the timer control word only when the reference timer value in the timer control word read from the timer control word storage unit and the reference timer value of the interval timer that generated the interrupt match; If the result is 1 or more, the timer control word containing the subtracted monitoring time value is returned to its original position in the timer control word storage section, and if the result of the subtraction is 0, the timer control word is returned to its original position in the timer control word storage section. means for notifying an external circuit of a timeout of the timeout; and after the notification, reading a timer control word indicated by the registered address pointer section, subtracting 1 from the registered address pointer section, and updating the timer control word; , means for storing in the timer control word storage section indicated by the update address pointer section, and updating the contents of the update address pointer section, so that the contents of the update address pointer section match the contents of the registered address pointer section. and a registration update control section having means for continuing the update processing of the timer control word until the time. 2. A flag indicating that the timer control word storage section is full is provided, and when the timer control word for timer registration is received, if the flag indicates that the timer control word storage section is full, an overflow occurs in the timer control word storage section in an external circuit. If a certain number or more empty areas are generated in the timer control word storage unit due to the update process, and if the flag indicates full, an external circuit is notified of the release of the overflow, and the flag is set. 2. The time monitoring circuit according to claim 1, wherein said registration update control section is provided with means for resetting.