JPS6030880Y2 - variable delay line - Google Patents

Description

[Detailed Description of the Invention] The present invention provides that the readout circuit is equipped with a CCD configured in a floating defension type, that the readout circuit is reset by a reset pulse, and that the readout signal read out from the readout circuit is The present invention relates to a variable delay line that sequentially performs sampling using sampling pulses.

CCD (Charge Coupled Device)
e) A large number of transfer electrodes are arranged on the surface of the semiconductor substrate via an insulating layer such as SiO2, and the presence or absence of charge existing in an unsteady state on the surface of the semiconductor substrate under this insulating layer is used as information for the above-mentioned transfer. This is an element that sequentially transfers data by driving pulses applied to electrodes.

CCDs having such a configuration have recently begun to be applied to imaging, memory, signal processing, and the like.

Note that as an example of this signal processing, it is possible to apply a CCD to a variable delay line, but in this case, transfer efficiency, frequency characteristics, linearity between input and output, etc. are important characteristic factors.

FIG. 1 shows a cross-sectional view of an example of a conventionally known two-phase CCD.

In FIG. 1, at the upper left end of the P-type silicon substrate 1,
An N+ region 2 is formed to constitute an input diode.

This N+ region 2 is connected to a signal source 3, and this signal source 3 is grounded via a bias power supply E1.

Further, an oxide insulating film 4 is formed on the substrate 1, and further on this oxide insulating film 4, input gates 5 and 6 and transfer electrodes 7a, 7b, 8 are formed in order from the left side to the right side.
a, 8b, - Song 1 lb, 12a1 Output gate 13 and reset gate 14 are arranged.

The input gate 5 is connected to a terminal 15, via which a sampling pulse shown in FIG. 2A for sampling the input signal is applied.

The input gate 6 is connected to the terminal 16, and this terminal 1
6, a DC voltage E2 of a predetermined value is applied.

Transfer electrode? a, 8a, . . . 12a are commonly connected to a terminal 17, and a transfer lock pulse φ□ shown in FIG. 2B is applied via this terminal 17.

Transfer electrodes 7b, 8b, . . . 11b are commonly connected to a terminal 18, and via this terminal 18,
The transfer lock pulse shown in is applied.

As is clear from FIGS. 2B and 2C, the clock pulses φ□ and φ2 have opposite phases to each other.

Further, the insulating film 4 under each transfer electrode has a step-like thickness change, so that a directional electric field is generated as shown by the dotted line 51 in FIG.

The output gate 13 is connected to a terminal 19, and like the input gate 6, a DC voltage E3 of a predetermined value is applied via this terminal 19.

The reset gate 14 is connected to a terminal 20, through which a clock pulse φ1 shown in FIG. 2B is applied as a reset pulse.

A reset drain 21 made of an N+ region is formed on the surface of the substrate 1 on the right side of the reset gate 14.

This reset drain 21 is connected to a DC power supply V via a terminal 50.

It is connected to the. Output gate 13 and reset gate 1
4, an N+ region 22 for forming an output diode is formed on the surface of the substrate 1.

This N+ region 22 is configured as a floating deflation, and is connected to the gate of the sensing MO3FET 24 of the output circuit 23.

This MO3FET24 is a source follower,
Its source is connected to the gate of MO3FET 25 for amplification.

This MO3FET25 is also a source follower,
Its source is connected to the drain of the sampling MO3FET 27 of the sample hold circuit 26.

The gate of this MO3FET 27 is connected to a terminal 28, and a sampling pulse S shown in FIG. 2A is applied via this terminal 28.

Also, the source of MO3FET27 is MO3FE for hold.
Connected to the gate of T29.

This MOS FET 29 also functions as a source follower, and its source is connected to the output terminal 30.

In the two-phase CCD configured as described above, an input signal from the signal source 3 is charge-injected into the N+ region 2, and this input signal is applied to the input gate 5 as a sampling pulse S (FIG. 2A). sampled by

The sampled signal charge is temporarily held in a potential well of a predetermined depth formed below the input gate 6, but when the transfer electrode 7a is turned on by the clock pulse φ1 (FIG. 2B), It is transferred to the potential well below the transfer electrode 7a.

Next, when the transfer electrode 7a is turned off and at the same time the transfer electrode 7b is turned on by the clock pulse φ2 (FIG. 2C), the signal charge is transferred to the potential well below the transfer electrode 7b.

Below, the signal charges are transferred to the transfer electrodes 8a, 8b...ll
The light is sequentially transferred below b and reaches the transfer electrode 12a.

At this time, the transfer electrode 12a is turned on by the clock pulse φ1, but at the same time, the reset gate 12a is turned on by the clock pulse φ1.
4 is also turned on by the clock pulse φ□.

For this purpose, an N+ region 2 is used to form an output diode.
The residual charges in the N+ region 22 are drawn toward the reset drain 21 side, and the N+ region 22 is brought into a reset state.

Next, the signal charge that has reached the transfer electrode 12a is transferred to the output gate 1.
3 and reaches the N+ region 22 which is in the reset state as described above, this signal charge is transferred to the N+ region 22.
This is read out as a change in the combined capacitance of the capacitance of the sensor MO3FET 24 and the gate-drain capacitance of the sensing MO3FET 24.

After this read signal is amplified by MO3FET25,
The signal is sampled and held by the sample and hold circuit 26, and taken out as an output signal from the output terminal 30.

Incidentally, in the two-phase CCD shown in FIG. 1, the clock pulses φ1. The duty ratio of φ2 is always set to 50%, regardless of changes in the frequency of these pulses.

Therefore, as the frequency increases, the clock pulse φ
1. The pulse width T1 of φ2 decreases, and conversely, as the frequency becomes lower, the pulse width T1 increases.

In short, clock pulse φ1. Even if the frequency of φ2 changes, only the proportion of the time axis changes, but this means that the pulse width T2 of the sampling pulse S shown in FIG. 2A and the trailing edge of the clock pulse φ are The same applies to the time width T3 between the pulse S and the leading edge.

Therefore, pulse width T2 and time +f+F'.

changes in accordance with the change in frequency.

On the other hand, when the CCD shown in FIG. 1 is used as a variable delay line, sampling pulse S and clock pulse φ1. φ
2 frequency is changed according to the desired delay time.

The present inventor believes that with such a variable delay line, changes in the frequency of the sampling pulse S and clock pulses φ1 and φ2 cause level fluctuations and gain fluctuations in the output waveform, especially in the high frequency region, and this causes input It was discovered that linearity between outputs was lost and stable frequency characteristics could not be obtained.

Furthermore, as a result of research to elucidate the above-mentioned deficiencies of the variable delay line and correct such deficiencies, the present inventor has developed a CCD according to the present invention, as will be explained in detail below. The time width between the trailing edge of the reset pulse for resetting the readout circuit and the leading edge of the sampling pulse for sampling the readout signal read out from this readout circuit is constant regardless of the frequency of these pulses. It has been found that the above-mentioned defects can be greatly improved by maintaining the temperature at

Next, embodiments of the present invention will be described with reference to FIGS. 3 to 6.

In the following embodiments, the structure of the CCD may be substantially the same as that shown in FIG. 1, so it will be explained with reference to FIG.

FIG. 3 is a block diagram of a clock pulse and sampling pulse forming circuit according to an embodiment of the present invention.

In FIG. 3, an input terminal 31 to which a clock pulse of a frequency corresponding to a desired delay time is supplied is connected to respective inputs of a delay circuit 32 and an inverter 33.

The respective outputs of the delay circuit 32 and the inverter 33 are connected to the inputs of an AND gate 34, and the outputs of this gate are connected to the respective inputs of the drive amplifier 35, the inverter 36, and the delay circuit 37. .

The output of the inverter 36 is connected to the input of the drive amplifier 38, and the output of the delay circuit 37 is connected to the input of the drive amplifier 39.

The respective outputs of the drive amplifiers 35, 38, 39 are connected to output terminals 40, 41, 42, respectively.

In the pulse forming circuit configured in this manner, the clock pulse a shown in FIG. 4A from the input terminal 31 is supplied to the delay circuit 32 and the inverter 33, and the clock pulse a shown in FIG.
A clock pulse b delayed by a time T4 as shown in FIG. 4B is obtained from the output of the inverter 33, and an inverted clock pulse C as shown in FIG. 4C is obtained from the output of the inverter 33.

These clock pulses b and c are supplied to an AND gate 34, and from the output of this AND gate 34, a clock pulse d having a pulse width T4 as shown in FIG. 4 is obtained.

This clock pulse d is amplified in the drive amplifier 35, and a clock pulse φ1 is obtained from the output terminal 40.

Furthermore, the clock pulse d is supplied to the inverter 36 and the delay circuit 37, and the lock pulse e as shown in FIG. 4E is obtained from the output of the inverter 36, and the clock pulse e as shown in FIG. A clock pulse f delayed by T5 is obtained.

The clock pulse e is amplified in the drive amplifier 38,
A clock pulse φ2 is obtained from the output terminal 41.

The q-tsuku pulse f is amplified in the drive amplifier 39, and a sampling pulse S is obtained from the output terminal 42.

The pulse width of the naori lock pulse φ□ and the sampling pulse S is determined by the delay time T4 by the delay circuit 32,
It is constant regardless of the frequency of clock pulse a.

Further, the time width between the falling edge of the clock pulse φ1 and the rising edge of the sampling pulse S is determined by the delay time T5 by the delay circuit 37, and is constant regardless of the frequency of the clock pulse a.

The clock pulses φ1, φ2 and the sampling pulse S obtained as described above are supplied to each terminal of the CCD shown in FIG.

That is, clock pulse φ1. φ2 is a transfer electrode via terminals 17 and 18 as a driving pulse. a, 8a,...
...12a and transfer electrodes 7b, 8b, ...
11b, respectively.

Furthermore, the clock pulse φ1 is supplied to the reset gate 14 via the terminal 20 as a reset pulse.

Further, the sampling pulse S is supplied to the input gate 5 via the terminal 15 as an input signal sampling pulse, and is also supplied to the gate of the MO3FET 27 via the terminal 28 as an output signal sampling pulse.

As described above, the input signal charge injected into the N+ region 2 for forming the input diode is sampled by the sampling pulse S, and this sampled signal charge is transferred to the clock pulse φ1. φ
2 and reaches the N+ region 22 forming the output diode.

The read signal read from the N+ region 22 is sampled and held in the output circuit 23, as described above, and then taken out from the output terminal 30 as an output signal.

FIG. 5 shows signal waveforms at various parts when the clock pulse and sampling pulse obtained from the circuit shown in FIG. 3 are used in the CCD shown in FIG. 1, and FIG. 5A shows the N+ Potential waveform in region 22, FIG. 5B
5C shows the reset pulse φ1, and FIG. 5C shows the sampling hold pulse S, respectively.

As described above, when the signal charge is transferred to the transfer electrode 12a, the N+ region 22 is reset by the reset pulse φ1 (FIG. 5B) applied to the reset gate 14.

Thereafter, by turning off the transfer electrode 12a and the reset gate 14, the signal charge is transferred to the N
+ led to area 22.

This operation process will be explained with reference to FIG. 5A. The potential of the N+ region 22 is reset to a predetermined level vR by a reset pulse φ□ just before the signal charge arrives, and gradually drops when the signal charge arrives.

The slope of its descent corresponds to the amount of signal charge, and in the middle of the slope of this charge signal, the sampling pulse S (Fig. 5C
) is sampled as shown by the dotted line in FIG. 5A.

Next, this sampled signal is sampled and held, so that an output signal having a waveform connecting the sampled signals is obtained from the output terminal 30.

As mentioned above, in this embodiment, the reset pulse φ1
In other words, the pulse width of the sampling pulse S is constant regardless of the frequency of the driving pulse φ1゜φ2, so the reset period and the sampling period of the input/output signal are always constant, and the reset pulse φ1 The time width between the falling edge of S and the rising edge of the sampling pulse S is also constant, and therefore the time from resetting to sampling the output signal is constant.

Contrary to the above case, if the time from resetting to sampling the output signal is not constant as in the conventional example shown in Fig. 3, the sampling position will change as shown by the arrow in Fig. 5A. shifts from side to side, and for this reason, even if the integrally detected charge signal is the same, the level of the signal obtained by sampling this charge signal will vary in accordance with the change in time.

However, in this embodiment, since the above-mentioned time is constant regardless of the frequency, the level of the sampled signal does not fluctuate as described above.

Furthermore, in this embodiment, as described above, since the reset period is constant, the reset state of the signal charges transferred to the N+ region 22 is always uniform.

Also, since the sampling period of input and output signals is constant,
The amount of input charge and the amount of output charge become independent of the frequency of the drive pulse.

Therefore, according to this embodiment, it is possible to effectively prevent level fluctuations and gain fluctuations in the output waveform due to changes in the frequency of drive pulses, reset pulses, sampling pulses, etc. A variable delay line with excellent linearity and frequency characteristics can be provided.

Although one embodiment of the present invention has been described above, the present invention is not limited to the above-described embodiment, and various modifications can be made based on the technical idea of the present invention.

For example, in the above embodiment, the pulse width of the clock pulse φ1 and the pulse width of the sampling pulse S are set to the same -T4, but these pulse widths can be made to be different. For example, the pulse width of the sampling pulse S is It may be smaller than the pulse width of the clock pulse φ□.

In this case, the circuit shown in FIG. 6 is combined with the AND of the circuit shown in FIG.
Connection point between gate 34 and inverter 36 and delay circuit 3
7.

Note that the delay circuit 45 and inverter 4 in the circuit of FIG.
6 and N■ agate 7 correspond to the delay circuit 32, inverter 33, and AND gate 34 in the circuit of FIG. 3, respectively.

Therefore, in the same way as in the circuit of FIG. 3, a clock pulse d having a pulse width of delay time T by the delay circuit 32 can be obtained from the clock pulse a, in the circuit of FIG. 0〈T6〈T
5) from clock pulse d' or clock pulse d having a pulse width of 5).

This clock pulse d' is supplied to the delay circuit 37 as in the case described above, so that a sampling pulse S having a pulse width T6 is obtained from the output terminal 42.

As described above, the present invention aims to reduce the time width between the trailing edge of the reset pulse for resetting the CCD readout circuit and the leading edge of the sampling pulse for sampling the readout signal read out from the readout circuit. is held constant regardless of the pulse frequency.

Therefore, according to the present invention, it is possible to effectively prevent the level of the signal sampled from the readout signal from fluctuating due to the change in frequency, thereby improving the linearity and frequency characteristics between input and output. be able to.

[Brief explanation of the drawing]

FIG. 1 is a cross-sectional view of an example of a conventionally known two-phase CCD, FIG. 2 is a waveform diagram of clock pulses and sampling pulses conventionally used to drive the two-phase CCD of FIG. 1, and FIG. 4 is a block diagram of a clock pulse and sampling pulse forming circuit according to an embodiment of the present invention, FIG. 4 is a signal waveform diagram of each part in the circuit of FIG. 3, and FIG.
A signal waveform diagram of each part when the clock pulse and sampling pulse obtained from the illustrated circuit are used in the CCD shown in FIG. 1, and FIG. 6 is a main part block diagram showing a modification of the circuit of FIG. 3. In addition, in the symbols used in the drawings, 5, 6...
・Input gate, 7a...12a ・Curve/Transfer electrode, 7b
...llb...Transfer electrode, 13...
Output gate, 14...Reset gate, 21.
. . . Reset drain, 23 . . . Output circuit.

Claims (1)

[Scope of utility model registration request] The readout circuit includes a CCD configured in a floating defension type, and sequentially resets the readout circuit with a reset pulse and samples a readout signal read out from the readout circuit with a sampling pulse. The variable delay line is configured such that the time width between the trailing edge of the reset pulse and the leading edge of the sampling pulse is held constant regardless of the frequencies of these pulses.