JPS6032094A - Electronic musical instrument - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to electronic musical instruments, and particularly to electronic musical instruments capable of simultaneous sound generation of multiple channels, which makes it possible to apply frequency modulation to each channel independently and The present invention relates to an electronic musical instrument that can independently output generated sounds.゛Conventional configuration and its problems Conventional vibrato generators have a configuration that applies frequency modulation, which is common to polyphonic electronic musical instruments.
In particular, even in an electronic musical instrument that uses two channels to generate sounds, such as that shown in Japanese Patent Application No. 118348/1983 entitled "Electronic Musical Instruments," the same vibrato is applied to the two generated sounds. Therefore, the vibrato effect was monotonous and had an artificial sound.

OBJECTS OF THE INVENTION It is an object of the present invention to provide a polyphonic electronic musical instrument, particularly an electronic musical instrument that can produce sound using a plurality of channels for one key, in which waveforms, amplitudes, and two-phase To provide an electronic musical instrument capable of obtaining a natural unsampling effect with spatial expanse by applying different independent frequency modulations such as and independently outputting a plurality of musical tones corresponding to the plurality of channels. It is something.

Structure of the Invention The electronic musical instrument of the present invention includes a plurality of frequency modulation data memories that store frequency modulation data, an address generation section that generates addresses for the frequency modulation data memories, and one frequency modulation data memory from among the plurality of frequency modulation data memories. a selector for selecting a frequency modulation data memory; a reference note clock generator capable of generating a plurality of note clocks;
a musical tone synthesis section that generates a musical tone corresponding to the note clock frequency and has an output path of a plurality of channels, and outputs data from the plurality of frequency skew data memories.

is added to the above-mentioned reference note clock generation section, independent frequency modulation is applied to the above-mentioned plural note clocks, and it is configured so that it can be output independently from the above-mentioned musical tone synthesis section, thereby obtaining a natural unsampling effect. be able to.

DESCRIPTION OF EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram of the electronic musical instrument of the present invention. o(1o1) is a keyboard section (KB), and (102) is composed of a tone tablet switch, a vibrato effect on/off switch, a glide effect on/off switch, etc. The operation unit (TAB), (1OA) is the central processing unit (CPU)
) is similar to those used in computers, (104) is a read/write storage device (random access memory called RAM)% (,105) is a C
A read-only storage device (read-only memory with RO
(call it M).

A ROM (106) stores waveform sample data for synthesizing musical tones, suppressing data for waveform interpolation, and the like. (107) is a musical tone generator t (1o8) that generates musical tones using the waveform sample data and control data stored in the ROM (1o6), and a filter that removes sampling noise (109) is an electroacoustic transducer. be.

Keyboard section (101), operation section (102), 0n (103)
.

The RAM (104), ROM (105) (106), and musical tone generator (1o7) are connected by a data bus and an address control line. The method of coupling the data bus, address bus, and control line in this manner is a well-known construction method mainly used in computer systems. Eight to 16 data buses are used, and data is transmitted and received on these bus lines not in one direction but in multiple directions in a time-division manner. A plurality of address codes, for example 16, are prepared, and usually the CPU (1o8) outputs the address code, and the other parts receive the address code. As the control line, a memory request line (MRKO), a request line (XORQ), a read line (100), a write line (100), etc. are usually used.

MRKQ indicates reading and writing memory.

10RQ indicates that the contents of the input/output device (Ilo) are to be retrieved, RD indicates the timing to read data from the memory or Ilo, and WR indicates the timing to write data to the memory or Ilo. An example of a microprocessor using such a control line is the microprocessor Z8O manufactured by Zilog.

Next, we will discuss the operation of the electronic musical instrument shown in Figure 1.
1o1) is configured such that a plurality of key switches are divided into a plurality of groups, and the on/off states of the key switches in the groups can be sent to the data bus all at once. For example, in the case of a 61-key keyboard, there are 10 groups of 6 keys (half an octave) each and 1
Divide the keys into 911 groups and assign one address code to each group. One of the above groups on the address line
When an address code indicating one key switch arrives and signals 10RQ and 11 are applied, the keyboard section (1o1) decodes the address code and outputs a 6-bit or Outputs 1-bit data to the data bus. These can be constructed using decoders, bus drivers and some gate circuits.

Of the operation section (102), the tablet switch can have the same configuration as the keyboard section (IQl).

(The 3PU (103) reads the instruction code from the address of the ROM (105) that corresponds to the internal program counter code, decodes it, performs arithmetic operations, logical operations, reads and writes data, and executes the program counter code. Operations such as jumping commands due to content changes are performed.The procedures for these operations are written in the ROM (105).First, the CPU (103) reads the data of the keyboard section (101) from the ROM (105). The command is read, and the codes indicating the on/off status of the six keys of the keyboard section (101) are captured for each group.Then, the pressed key codes are transferred to the finite channels of the musical tone generator (107). The musical tone generation data corresponding to the assigned key code is transmitted.

Next, the KCPU (103) sequentially reads a group of instructions from the ROM (105) for importing data from the operation section (102), decodes them, and sets the address code and control (IIORQ and RD) corresponding to the operation section (102). and causes the data bus to output a code representing the state of the switch of the operation unit (1o2).

Read into 0PU (103). , selects a tone and generates predetermined effect control data based on the data read into the CPU (103), and stores the tone selection data in the %ROM (106) and the effect control data in the musical tone generator (107). Send out. The method of allocating the pressed key code to a finite channel of the tone generator (107) is known as a generator assigner function.

The musical sound generation section (107) generates musical sound synthesis data ROM based on the musical sound generation data supplied from the CPU (103).
(106) takes in predetermined waveform sample data and control data, performs waveform interpolation processing, and generates a musical sound waveform.
Electroacoustic transducer (109) via filter (108)
generate musical sounds.

FIG. 2 shows a time chart when data is supplied from the CPU (1o3) to the tone generator (107).

A port address is supplied to the address bus, and musical tone generation data and effect data are supplied to the data bus. And control signals l0RQ and WR
At the timing when the signal changes from a logic low level (hereinafter abbreviated as "o") to a logic high level (hereinafter abbreviated as "tt1"), the contents of the data bus are transferred to the channel specified by the port address.

Next, various types of data supplied to the musical tone generating section (107) will be explained.

Table 1 Table 2 Table 3 Table 1 shows the I10 boat address and the contents of various data. The I10 port address is displayed in hexadecimal.

The data corresponding to I10 port addresses (00)16 to (07)+6 are musical tone generation data that can be generated for eight channels, that is, for eight tones. The I10 boat address (08)+6 is sustain data that specifies the attenuation characteristic of the envelope signal. The I10 port address (09)16 is damper data that becomes valid when the envelope characteristic is piano type, and, like the sustain data, specifies the attenuation characteristic of the envelope signal. Ilo port address (OA) +6 is beat data that specifies the frequency shift when two musical tones are generated. The I10 port address (OB) 16 is effect control data, consisting of vibrato on/off signals, glide on/off signals, and the like. I10 port address (OC
)<b is vibrato select data, which is data for specifying one vibrato data from among a plurality of vibrato data.

Table 2 shows the composition of the musical tone generation data. Bit positions DQ to D3 are note clock designation data that designates the scale frequency. Bit positions D4 to D6 are waveform sample number designation data that designates the generated sound range. Bit position D
Reference numeral 7 indicates a key on/off signal accompanying the on/off operation of the key switch, which is 0' when off and -' when on.

Table 3 shows the code contents of the waveform sample number designation data 5Do-8D2 and the number of samples in one cycle of the waveform designated by the code. The waveform sample number specification data SD is (ooo
)z to (111)2, eight types of waveform sample numbers can be specified, and in this embodiment, 512 samples to 4 samples are specified.

Table 4 Table 6 Table 4 shows the relationship between the contents of the chord represented by the note clock designation data NDo-ND3 and the specified scale specified by the code.

Table 5 shows the composition of the effect control data. The pit position Do is the vibrato on/off signal VIB.

When the vibrato on/off switch in the operation unit (102) is off, it is "0", and when it is on, it is "11".

Pit position D1 is delay vibrato on/off signal D
VIB is a delay vibrato effect control signal, which is 9IO" when the delay vibrato on/off switch in the operation unit (102) is off, and 1" when it is on.

The pit position D2 is the glide on/off signal GL, and when the glide switch in the operation section (102) is off, the position is °'0''.
, becomes "'1" when it is on.

Pit position D3 is organ type/piano type designation signal OPS
This specifies the envelope characteristic, which is t10'' for an organ type and tt1'' for a piano type.

Pit position D4 is damper on/off signal DMP.

This is valid only when the envelope characteristic is a piano type, and is tto'' when the damper is off, and 11111 when the damper is on.

Pit position 11g is the generator assigner operation mode signal GAM, which is a designated signal when using 2 musical tone generation channels with 1 key. If the GAM signal is "0", 1 key uses 1 channel (8 tone generation). So, in the case of °11", 1 key uses 2 channels (4 notes are generated).
Channel and (N+4) channels generate musical tones corresponding to one key.

(N = 1 + 2 + 3 * ') Regarding the generator assigner operation mode, please refer to Japanese Patent Application No. 53-118.
348 ``Electronic Musical Instruments''.

The pit position D6 is the no-fu vibrato on/off signal HVIB, which is tt on when the no-fu vibrato on/off switch of the operation unit (102) is off, and is "1" when it is on.

The pit position D7 is the channel independent vibrato on/off signal switch vIB, and is 10" when the channel independent vibrato on/off switch of the operation unit (102) is off, and 1" when it is on.

FIG. 3 is a configuration diagram of the musical tone generator (107).

In Fig. 3, (301) is the main oscillator, (302) is the sequencer that controls the operation contents of the musical tone generator (10A), and (303) is the input that latches various data supplied from CPt1 (103). Register section, (aO4) is a timer, (305) is a comparison register section, (306) is a frequency data processor (hereinafter abbreviated as FDP) that generates frequency data corresponding to the frequency to be generated (307)
is a waveform data processor (hereinafter referred to as W) that performs waveform interpolation processing.
(abbreviated as DP)% (308) is musical tone synthesis data ROM (
106) is a data read processor (hereinafter abbreviated as DRP) that reads waveform sample data and control data, etc. (3os) is a read pulse forming unit that generates a pulse signal with a predetermined pulse width. (30
7) A calculation request flag generation unit that requests calculation processing to the DRP (30B) and the like.

(311) is a digital/analog converter (hereinafter abbreviated as DAC) that converts digital signals to analog signals.
(312) consists of two real analog switches and one capacitor per channel, and an analog buffer memory section (313), (314) that holds analog signals.
) is an integrator.

Here, the waveform interpolation method executed by the WDP (207) will be explained.

As a waveform interpolation method, 1 + 1 (1 = Or 1 + 2 +
. . . , l-1), one cycle of the musical waveform repeats M times, and the waveform sample f(Xi, n
) and f (Xi+1.n), the virtual sample value f (Xi, m, n) 'c Let's virtually calculate the waveform sample value of the virtual sample point using the interpolation operation and find an approximate value. That is. The interpolation formula is shown below.

f (Xi, m, n) = (f (Xi + t, n) - f (
Xi, n))i is a sample position extracted by dividing the sample and is a waveform number. (1-0+ 1+ 2+=・y
) m is M times 9 times between waveform number i and i+1.
It represents the position in the middle of a return transition. (1
fi==Q, 1.21...r M 1 )n is,
The waveform sample number is the sample position obtained by dividing one cycle of the musical sound waveform into N parts. (n=0・1.2...,N-1) The operations around the WDP (207) and DRP (208) are described in detail in Japanese Patent Application No. 67-2314821 "Music Sound Generator". .

In the above configuration, (304), (305), (soe
).

(310) constitutes a note clock generating section that determines the tone to be produced.

Further, in the above configuration, (307), (30B), (31
1)+(312) constitutes a tone synthesis section, which synthesizes musical tones based on the output signal of the note clock generation section.

In addition, input register section (SOS) t comparison register section (
305), FDP (306), WDP (307),
The procedure for processing the DRP (so8) and the calculation request flag generation unit (310) is determined by the sequencer (302).

When musical tone generation data is supplied from the CPU (103) to a predetermined channel, for example, channel 1, the sequencer (302
) from the input register section (303) to the FDP (306), WDP (307),
Musical tone generation data is supplied to the DRP (308). Then, in DRP (308), musical tone synthesis data R
Read waveform sample data and control data from OM (106). Then, f (Xi, n) shown in equation (1) is data WDI, and f (Xi++, n) is data WD
It is supplied to WDP (so7) as I. Furthermore, WDP (3
07). When the final waveform data is reached, the WICF signal indicating the final waveform data is sent to WDP (307).
supply to.

The WDP (307) receives the data WD1. which is supplied from the DRP (308). WDI, using MLP t-, (1)
It performs waveform calculation processing according to the equation and supplies it to the DAC (311). Then, in the DAC (311), WDP (ao7
) converts the digital signal supplied from the device into an analog signal.

In the analog buffer memory section (312), analog charges are stored.

On the other hand, in the FDP (306), the input register section (3O3
) Frequency data is generated based on the musical tone generation data supplied from
is supplied to the register corresponding to . Then, the data supplied to the comparison register (305) and the timer (304)
Performs comparison processing with time data supplied from
When a match is detected, a match pulse is read out and supplied to the read pulse forming section (309) and calculation request flag generating section (310).

Then, a read pulse forming section (309) generates a read signal with a predetermined pulse width and supplies it to the analog buffer memory section (312). The charge stored in the capacitor corresponding to cell 1 in the analog buffer memory section (312) is transferred to the integrator (
313).

The calculation request flag generation unit (alO) generates a human waveform sample, that is, a virtual sample point f (Xi, m, n++
) generates and maintains a computation request flag.

Then, when the processing timing reaches channel 1 again, the calculation request flag has been generated, so waveform interpolation processing is performed in the same way as described above, and the analog buffer memory section (3
Charge is stored in the capacitor in 12). Thereafter, waveform interpolation processing is performed on the calculation request flag It-, + to generate a musical tone waveform.

Note that the charge stored in the capacitor is f (Xi, m,
n−+) and the waveform sample value f (Xi, m,
This corresponds to the difference from n). and an integrator (313),
(314) The waveform sample value f (X
i, m, n) will be restored. Analog buffer 1 memory section (312'), integrator (313), (31
4) Regarding peripheral operations, see Japanese Patent Application No. 57-126413.
1 waveform readout device”.

FIG. 4 is a block diagram of a specific example of the sequencer (302). In the figure, (401) is a two-phase lock generation unit that generates two-phase lock signal φ1 and signal φ2, ←4o2) is a hexadecimal counter that determines the operation sequence for one channel, and (403) is the current calculation. A counter that generates the channel code being processed. ('404) is a ROM in which operating procedures are stored.

(405) is a decoder. Figure 6 shows the sequencer (3
02) is shown.

A master clock (MCI) signal is supplied from the main oscillator (aol) to the two-phase lock generation section (401).

The two-phase lock generating section (401) generates a two-phase lock signal φ1.% as shown in FIG. The 0 signal φ1 which generates φ2 is supplied to the hexadecimal counter (402) and the counter (403).

The hexadecimal counter (402) has a 4-pit configuration, and the count-up process is performed at the timing when the signal φ1 changes from "o" to "frost", and the output signal becomes (1111).
)2, and then when count amplification is performed, (0101
) is set to 2. As a result, the decimal counter (40
The output signal of 2) is in 11 states, i.e. (0101)2
~(1111)2. This is used as a command step signal.

The counter (403) has a 3-pit configuration.

The output signal of the decimal counter (402) is (1111)2
A count-up process is performed every time the value changes from (olol)2 to (olol)2. As a result of this, the output signal of the counter (403) is in 8 states, that is, (000)2 to (111)2
becomes. Use this as the channel code.

Table 6 shows the relationship between the musical tone generation data supplied from the CPU (103) and the channel code of the musical tone generating section (107).

The sixth table ROM (404) reads out the instruction code based on the instruction step signal supplied from the hexadecimal counter (402) and supplies it to the decoder (405). Decoder (405
The main unit decodes the instruction code supplied from the ROM (404) and supplies processing control signals to each section.

As a result, the calculation time per channel is 2.76 μs.
Therefore, each calculation process is performed in 11 instruction steps. Then, the calculation timing is repeated every 22 μs.

FIG. 6 shows a configuration diagram of a specific example of the analog buffer memory 1 (312). In the figure, (600) is the input terminal % (60
1), (602) are output terminals, (eos) to (618
) are analog switches, 01 to C8 are capacitors, and signals W1 to AW8 supplied to the gate inputs of analog switches (603) to (610) are WDP (307
). In addition, analog switch (61
The signals R1 to AR8 supplied to the gate inputs of 1) to (618) are supplied from the read pulse forming section (309).

The analog signal converted by the DAC (311) is input to the input terminal (
eoo) and analog switches (603) to (6
10). If the data corresponds to channel 1, only the analog switch (803) is turned on, and the charge corresponding to the analog signal applied to the input terminal (600) is stored in the capacitor C1.

Thereafter, the read pulse R1 corresponding to channel 1 is supplied from the read pulse generator (309) to the gate input of the analog switch (611).

The charge stored in the capacitor C1 is transferred to the output terminal (601
) to the integrator (313).

Analog switches (eos) to (elo) are WDP (3
Because it is synchronized with the operation timing of 07,).

Multiple units cannot be turned on at the same time. Since the analog switches (610) to (618) are turned on in synchronization with the musical scale frequency, a plurality of analog switches (610) to (618) can be turned on at the same time.

Note that the outputs of the readout analog switches (611) to (614) corresponding to channels 1 to 4 are supplied to the integrator (313) via the output terminal (602) as described above, and The outputs of the readout analog switches (615) to (61B) corresponding to 8 are as follows:
It is supplied to the integrator (314) via the output (eos). Therefore, the musical tones corresponding to channels 1 to 4 and the musical tones corresponding to channels 5 to 8 are output through independent signal paths.

FIG. 7 is an internal operation timing chart of the musical tone generator (307). FIG. 7 shows the timing for four channels.

Explanation of abbreviations in the diagram CRF is a calculation request signal for each channel.

Then, the request start point is the comparison register. It is synchronized with the coincidence signal supplied from the unit (305).

That is, the scale frequency For example, C If it is a musical scale, 0 occurs every 59.74 μs. CLC indicates waveform calculation timing.

DACj indicates the timing at which charge is stored in the capacitor in the analog buffer memory (312) via the DAC (311)k.

OTC is the timing when the charge stored in the capacitor in the analog buffer memory (312) is supplied to the integrators (313) and (314), and like CRF, it is generated in synchronization with the scale frequency. .

The time chart of channel 1 will be explained.

The calculation timing corresponding to channel 1 is determined by the sequencer (3
02), and as shown in the figure, calculation timing occurs every 22 μs.

(2) Signal CRF1 is generated in the middle of channel code 1. Waveform interpolation processing and frequency data updating are not performed at the generated timing.

■...Signal 0TC1 is generated at the same time as signal 0RF1 is generated.
is generated, and the charge on the capacitor C1 in the analog buffer memory (312) is supplied to the integrator (313). The pulse width of the signal OTO is about 2 μs.

(2) When the channel code becomes 1 again, reading processing of waveform sample data, waveform interpolation processing, frequency data updating processing, etc. are performed.

■...When the arithmetic processing of channel 1 is completed, the signal DA
C1 is generated, and charge is stored in the capacitor C1 via DA(3 (311)).

■...When the arithmetic processing of channel 1 is completed, the signal CR
Reset F1 and cancel the calculation request.

■...Similar to the above ■, at the timing when the signal CRF1 is generated again, at the timing of the above ■, the capacitor C
The charge stored at 1 is supplied to an integrator (313).

From then on, as described above, each time the signal CRF is generated, 1
The temporary phase waveform sample value calculation process and the frequency data update process are performed, and the waveform calculation result is transferred to the integrator (313) in synchronization with the generation timing of the signal CtRF, that is, the musical scale period.
)l (314).

Regarding the relationship between the calculation cycle and the scale period, it is sufficient that the calculation timing of the same channel can be performed twice within the minimum scale period and that the calculation result can be stored in a capacitor in the analog buffer 1 memory section (312).

That is, it is sufficient to provide calculation timings corresponding to 10 channels within the minimum scale period in consideration of vibrato, glide, etc.

Description of how to generate pitches Regarding notes, a clock signal corresponding to a 12-tone scale is generated. As for octave-related pitches, octave-related intervals are generated by changing the number of samples in one cycle of the musical sound waveform stored in the musical tone synthesis data ROM (106).

Assuming that the Co sound (32,708H2) is 612 samples.

The note clock signal is 32.7081~IzX51
2 samples≠16.74 klb. Table 7 shows the note clock frequency, and Table 8 shows the number of waveform samples and the octave relationship.

Table 7 9 at = 8-00096 Melt 8 Explanation of how to generate the phonetic scale period Figure 8 shows the comparison register section (30
5) shows the transition of frequency data supplied.

The timer (304) is composed of a 10-pit binary counter, and when the output status is expressed in hexadecimal, it is (000
)16 to (3FF)16, fx sequentially counts up, from (3FF)+6 to (000)+6 again, and from (000)16 to (ay F)16 is the signal MCI supplied from the main oscillator (301). will be returned based on. In other words, the repetition period TR of the timer (304) becomes as follows.

=127.98 μS The output data transition state of the timer (304) is described as timer output data in FIG.

The method of generating the scale period is to compare the output signal of the timer (304) with the frequency data supplied from FI) p (aoe), and if a match is detected, a match pulse is sent from the comparison register section (SOS). .

The generation cycle of the matching pulse becomes the scale cycle of the scale to be sounded.

As shown in FIG. 8, a note clock signal can be generated by updating one frequency data.

In other words, the arithmetic processing shown in the formula below is performed using FDP (306
).

NFD=MOD(OFD+FD, TDmax) −・−
...(3) NFD is new frequency data.

OFD is frequency data before update.

PD is scale data determined by the scale of one occurrence.

'rl)max is the number of output states of the timer (ao, a). In this example? 'l) wax is 210 or 1o24.

Table 9 shows scale data PD corresponding to the 12-tone scale.

Table 9 Numerical representation is in decimal.

FIG. 9 is a block diagram of a specific example of the FDP (306). In FIG. 9, (902) indicates that the generator assigner operation mode signal GAM is 61" and the channel code is "2".
(OBD), (901) is a cent scale data generator (hereinafter referred to as CPD) that generates scale data (CPD) expressed in cent scale. It consists of a ROM that stores cent scale data (abbreviated as the OPD generator), and contains note clock specification data (HD), waveform sample number specification data (SD), and organ type/piano type specification signal (OPS). The CPD based on the above information is selectively generated. (904) is a glide signal generation unit that generates a glide signal.

(906) is an index converter that converts the frequency value expressed in centimeters into frequency data directly proportional to the frequency;
06) is an arithmetic unit, (907) is a latch (referred to as muL),
(908) is a latch (designated as BL), (909) is an adder (designated as FA), (910) is a node, (911)
) is a gate. (912)+ (913)y(91
4) is the pass line, (912) is FA Babas (913
) is the FB bus and % (914) is the FC bus.

In addition, beat data CBD, vibrato data CVD,
Glide data CGD is also expressed in cents.

Structure of various data Cent pitch data (OPD) It is composed of 11 bits, with the upper 4 bits representing 12-tone equal temperament, and the lower 7 pits representing each point of the chromatic scale divided into 128 equal parts.

Heat data (CBD), vibrato data (cvn)
.

Glide data (CGD) Each bit has an 8-bit configuration, uses two's complement representation, and has a resolution that divides the chromatic scale into 128 equal parts. It also represents positive and negative beat components, vibrato components, and glide components.

Description of Vibrato Signal Generating Section (903) FIG. 10 shows a configuration diagram of a specific example of the vibrato signal generating section (903). In the figure, (1001) is a vibrato ROM that stores a plurality of vibrato data CVD, (1002) is a vibrato address register that stores address data for reading out the vibrato data stored in the vibrato ROM (1001), (1003) is a gate s (1004) which supplies the output signal vibrato data cvn of the shifter (1003) to the FB bus by the signal RDCtVD.
1005) are the signals 1cD, VIB, [DVIB,
The vibrato signal generator (90
Condition setting section s (1006) for setting the operating conditions of 3)
is the selector, (1oo7) is the gate%, and (1oo8) is the mND gate.

(1oo9) indicates that the channel independent vibrato signal (IVIB) supplied from the input register section (303) is 11"
This is a selector that selects channel code 2 (ClO2) for the lower 1 bit of vibrato select data (YBD) when ``0'', and outputs data VBD as is when it is ``0''.

FIG. 11 is a data map diagram of the vibrato data memory stored in the vibrato ROM (1001). The vibrato data has a structure of 2048 words with 8 bits per word, and is read out using the lower 11 bits of the 14-pit vibrato address data stored in the register (1002) as address data. The vibrato ROM (1001) is supplied with the 11-bit address data and the lower 4 pits of the vibrato select data VBD supplied from the input register section (SOa) as select data. Therefore, by the vibrato selection data VBD, the vibrato R
One of the 16 vibrato memories stored in OM (1oo1) is selected. Register (1002)
The vibrato address data stored in the vibrato address data has a 14-pit configuration, and the lower 11 bits are stored in the vibrato ROM (vibrato) ROM (1
The address data is 001), and the upper 3 bits are shift data of the shifter (1ooa). Chic (10
03) is the vibrato ROM (1) based on the shift data.
This is to control the amplitude of the vibrato data CVD supplied from oo1). The relationship between the shift data VSFD and the output data 08FD of the shifter (1003) is as follows.

VSFD=(ooo)2-・-08FD=(00)+6
, V8FD=(001)2-08FD=(CVD/64
)a vsFD=(010)2.08FD=(CVD/
32), -・Song, V8FD=(110)2-008FD
=((VD/2), V8FD=(111)2-013F
D=(cvn) The condition setting section (100s) sets the following operating conditions.

This is the case when the vibrato off vibrato on/off signal VIB is It o '1, and the output of the game (1006) is forced to always be (
00), 6. Then, shifter (100a)
The shift data of is always (ooo)2. As a result, the output data of the shifter (100s) becomes (00)16. In other words, the vibrato data CVD is always (00)
It becomes 16.

Vibrato on vibrato on/off signal vIB is dragon 1'' and signal DVI
When B is "o", the vibrato is on. The address data stored in the register (1002) is supplied to the gate (1007) and shifter (1003). Note that the upper three bits of the address data, that is, the shift data, are forcibly set to (111)2. Then, the great sword of the gate (1004) has a vibrar) ROM (1001).
) (vibrato data cvn) will be supplied as is.

When the vibrato is ON, the generator assigner operation mode signal CA is supplied from the input register section (303).
When M reaches tJ'', two channels are activated for one key press, and the same vibrato is applied to the two channels. However, the center frequency of the vibrato of the two channels is determined by the beat data (OBD). There is a difference specified by .

About half vibrato Half vibrato means that in the generator assigner operation mode, that is, the mode in which two channels are used for one key, vibrato is added to the sound of one channel, and vibrato is added to the sound of the other channel. This mode does not add vibrato.

In this embodiment, the above-mentioned ivy (1
003) to prohibit the output of biprado data.

As mentioned above, the shifter (100a) receives shift data V.
When 8FD and output data are 08FD, the following relationship exists.

V8FD=COOO)2-...08FD=(oo),
6V8FD=(111)2...-08FD=(
CVD) In other words, when VSFD=(000)2, the output of vibrato data CVD is prohibited and V8FD==(111)
When z, output cvn as is.

The operation of half vibrato mode will be explained below. Half vibrato F on/off signal HV when vibrato is on
When XB becomes I'1'', channel code 2 (ClO2
) is 110”, F through the gate (1006)
The upper 3 bits of the vibrato address data supplied from the C bus, that is, the shift data vsyn, are forced (
111) 2, the output data of the vibrato ROM (1001) is supplied as is to the FB bus.

Channel code 2 (0HO2) ``1'' +7)
(!: @, above'/7) f - evening V8FD negative forced K (000) z" (, FB Babas 5oo) 16
be supplied. Therefore, the relationship between channel codes and musical sound generation channels is shown in Table 6, so the sounds corresponding to channels 1 to 4 will have vibrato, and the sounds corresponding to channels 6 to 8 will have vibrato. It doesn't cost anything. Furthermore, when the generator assigner operation mode is on, of the two notes produced for the %1 key, one has vibrato and the other does not.

About channel-independent vibrato Channel-independent vibrato refers to the generator assigner operation mode described above, which is a mode in which two channels are used for one key, and the two generated tones have independent amplitudes, two phases, and waveforms. This mode adds a vibrato with .

In this embodiment, channel independent vibrato is realized by selecting different vibrato data memories on the vibrato ROM (1001) depending on the channel code.

The operation will be explained below.

When the channel independent vibrato signal Iv is “0”, the vibrato select data VBD is the selector (1ooe)
The vibrato data memory specified by the data VBD added to the vibrato ROM (1001) is selected from the vibrato ROM (1oo1) through the vibrato ROM (1001).

When the channel independent vibrato signal IVIB is t1'',
The vibrato select data VBD includes select, ta(1o
o9), LSB only, channel code 2 (C
lO2).

The relationship between the channel code and the tone generation channel is as shown in Table 6.

Therefore, two vibrato data memories on the vibrato ROM (1001) are alternately selected in response to changes in 0HC2. When the above-mentioned channel independent vibrato is turned on when the generator assigner operation mode is on, different vibratos are added to two generated sounds corresponding to one key.

Figure 12 shows the data stored in the Vipler ROM (1001).
-J-/2 Ishi #71% jm+-k k □
□ LA-p address, vertical axis represents data. VBD = (00) 16 (i') when (&) knob -
taka, VBD=(01)16 (7) When the data in (b) is selected.

When the vibrato ROM (1001) has vibrato data as described above, when the generator assigner operation mode is on and the channel independent vibrato is on, the waveform shape and frequency amplitude are equal and the phase is equal for one key press. Different vibratos will be applied to the two generated sounds separately.

When the delay vibrato vibrato on/off signal YXB and the delay vibrato on/off signal DVIB are "1", a delay vibrato state is entered. 8 channel key on/off signal K
When any one of the key on/off signals KD turns on from the off state of all D, the address data is changed to (oo
o) Control the gate (1006) t'' so as to set it to +6.

Then, in Schick (1003), the vibrato data CvD amplitude control 6
m(o, OvD/eat OVD/82°OVD/1e
, cvD, /8. OvD/4. OvD/2.0VD) is performed. Then, when the shift data becomes (111)2, the shift data is forcibly set to (111)2 as in the vibrato-on state. The address data stored in the register (1002) is gated by the signal RDVAD supplied from the sequencer (302) (1007).
) is supplied to the FB bus.

The address data added by the calculation unit (906) is
The rising edge of signal φ2 is determined by the signal WRVAD.
It is stored in the register (1002) from the C bus. Also,
Vibrato ROM (1oo1
) The vibrato data CvD stored in '/71
(1003) + FB bus is supplied via the gate (1004).

Explanations of the symbols listed in Table 10 are as follows.

The program b latches the data supplied to the %FFA bus at the falling edge of the signal φ2.

BL latches the data supplied from the FB bus at the falling edge of signal φ2.

CRAL is an instruction to clear Latchim L by Jll of signal φ2.

Mu DDI is +t1″ to the carry manpower of FA (909)
An instruction to add.

TOM is an instruction to supply the results of arithmetic processing in the FA (909) to the FA bus.

RDOPD is an instruction for supplying cent pitch data epn2y generated by the %C1PD generation unit (901) to the epn2y user node.

RDCBI) is an instruction to open the gate of Beat Game (902) and supply FB Babas Beat CBD.

RDCV[ is an instruction 0 for supplying vibrato data cvn generated by the vibrato signal generation unit (903) to the FB bus. RDCGD is an instruction for supplying glide data CGDt-FB bus generated by the glide signal generation unit (eo4).

RDICIP is the I converted in the index converter (906).
Instruction to supply CIP(OPD) to FA bus.

RDΔIEIP is an instruction to supply ΔEIP(CPD)iFB(x%C) converted in the exponent converter (eo5).

RDFD is an instruction to read the daily frequency data Ov'D from the comparison register section (ao5) 75 and supply it to the FB bus.

RDVAD is an instruction to supply the contents of the vibrato address register (1002) in the vibrato signal generator (903) to the FB node.

RDCAD is a command to supply glide address data from the glide signal generator (904) to the iFB node.

The WRY module D stores the result of the calculation in the FA (909) in the vibrato address register (1002) in the vibrato signal generator (903) at the rising edge of the signal φ2.

WRGAD is an instruction to write the result calculated by FA (,909) to the glide signal generating section (904) at the rising edge of signal φ2.

WRICXP is an instruction to write the result calculated by FA (909) to the exponent converter (905) at the rising edge of signal φ2.

WRFI) is an instruction to write the result of the operation in 'Fm (909) to the comparison register section ('306) at the rising edge of signal φ2.

Note that the state 11 occurring in the decimal counter (402) in the sequencer (302) shown in FIG.
This corresponds to command Step 11 shown in the table.

In step 1 of the vibrato address increment processing instruction, the vibrato address register (100
2) The address data stored in latch BL (90
Write in B).

Then, in instruction step 2, +1 is added to the vibrato address data V? and stores the addition result in the vibrato address register (102) again.

In addition, vibrato period 1 is 6-3Hz (159m!1
), at the calculation timing of channel code 1, +1 increment processing is performed at a frequency of once every four times. By setting the vibrato address length to 1792, a cycle of 6.3 Hz can be achieved.

fvXB=1/(22μ5x4x1792)≠6-3
1 Effects of the Invention The electronic musical instrument of the present invention includes a plurality of frequency modulation data memories that store all frequency modulation data, an address generation section that generates addresses for the frequency modulation data memories, and one frequency modulation data memory selected from among the plurality of frequency modulation data memories. a selector for selecting one frequency modulation data memory; a reference note clock generator capable of generating a plurality of note clocks;
It includes a musical tone synthesis section that generates a musical tone corresponding to the note clock frequency and has a plurality of channels of output paths.

The output data of the multi-frequency modulation data memory is added to the reference note clock generator, and the plurality of note clocks are subjected to independent frequency modulation and outputted independently from the musical tone synthesizer. can be,
In particular, in electronic musical instruments that can produce sound using multiple channels for one key, it is possible to apply independent frequency modulation of different waveforms, such as amplitude and two-phase modulation, to multiple musical tones corresponding to the multiple channels. Since the above-mentioned multiple musical tones can be output independently, it is possible to obtain a natural unsampled effect that has spatial expanse and does not produce unnatural beats.

[Brief explanation of drawings]

FIG. 1 is a block diagram of the implementation 911 of the electronic musical instrument of the present invention, and FIG. 2 is a block diagram of the musical tone generator (10
7) Time chart diagram when supplying data, 3rd
The figure is a block diagram of the musical tone generator (1o7), Figure 4 is a block diagram of a specific example of the sequencer (302), Figure 5 is an operation time chart of the sequencer (302), and Figure 6 is the analog rough memory. 7 is an internal operation time chart of the musical tone generating section (107), and FIG. 8 is a diagram of the frequency data supplied from the FDP (306) to the comparison register section (305). Transition chart, No. 9
The figure is the configuration diagram of FDP (306) - concrete flj, No. 10
Figure 11 is a block diagram showing a specific example of the vibrato signal generating section (903), Figure i11 is a data map diagram showing the contents of the pibbler FROM, and Figure 12 is a diagram showing a specific example of vibrato data. (101)...Keyboard section, (102)...
・Operation section. (1OS)...Central processing unit% (104)
...RAM. (1Q15)...ROM, (106)...
...Musical sound synthesis data ROM, (107)...
Musical tone generator, (301)... Main oscillator% (3
02)...Sequencer, (303 units...)
Input register section, (304)... Timer, (
306)... Comparison register section, (306)...
...Frequency data processor% (307)...
...Waveform data processor. (30B)...Data read processor s (
309)... Read pulse forming section, (310
)...Calculation request flag generation section, (311)...
...DACl (312) ...Analog buffer 1 memory section, (313) ...Integrator% (9
01)...OPD generation section, (902)...
Beat data gate, (903) Vibrato signal generator, (904) Glide signal generator, (906) Index converter, (90
6)......Calculation section% (1001)...
Vibrato ROM, (1oo9)...Selector. Name of agent: Patent attorney Toshio Nakao and 1 other person 1st
Figure 2] Figure 11 Figure 2

Claims (1)

[Claims] (1) A plurality of frequency modulation data memories that store frequency modulation data, an address generator that generates addresses for the frequency modulation data memories, and one frequency modulation data memory selected from the plurality of frequency modulation data memories. a reference note clock generation section that generates a plurality of note clocks, a musical tone synthesis section that generates a musical tone corresponding to the note clock frequency and has an output path of a plurality of channels, and the plurality of frequency modulation data memories. The electronic musical instrument is characterized in that the output data of is added to the reference note clock generating section and independent frequency modulation is applied to the plurality of note clocks so that independent musical tones can be output from the musical tone synthesizing section. @) The electronic musical instrument according to claim 1, wherein the note clock generating section generates a plurality of channels of note clocks in response to one key depression.