JPS6032097A - Vibrato addition device - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a vibrato adding device for an electronic musical instrument, which has a particularly simple configuration, is capable of changing the vibrato frequency while preserving the vibrato waveform, and is capable of changing the vibrato frequency while preserving the vibrato waveform. Regarding a vibrato adding device that allows you to select.

Conventional configuration and its problems Conventionally, vibrato adding devices have been configured to perform analog frequency modulation on the main oscillator, so in order to change the vibrato frequency, it is necessary to change the frequency of the modulation signal. Therefore, the scale of the modulation signal generation circuit is large and the output frequency thereof is unstable.

Furthermore, a method has been proposed in which the vibrato frequency is changed by changing the read address length in a digital vibrato adding device that includes a vibrato data memory. Although this method has the advantage of a simple configuration, it has the disadvantage that the vibrato waveform also changes as the vibrato frequency changes.

Furthermore, since a portion of one vibrato data memory is used, it is not possible to arbitrarily select a vibrato waveform.

OBJECTS OF THE INVENTION An object of the present invention is to provide a vibrato adding device that has a simple configuration, can change the vibrato frequency while preserving the vibrato waveform, and can select an arbitrary vibrato waveform.

Structure of the Invention The vibrato adding device of the present invention includes a plurality of vibrato data memories that store a plurality of types of frequency modulation data, an address generation unit that generates an address for the vibrato data memory, and a vibrato adding device that stores a plurality of vibrato data memories. a vibrato data select section for selecting one vibrato data memory; a note clock generator capable of applying frequency modulation according to the output data of the vibrato data memory; and an address length control for controlling the address length of the address generation section. A vibrato waveform of an arbitrary frequency and an arbitrary shape can be generated by controlling the address length generated by the address generating section and selecting a vibrato data memory corresponding to the address length using the vibrato data selecting section. It has a simple structure and can generate a vibrato waveform of any frequency and any shape.

DESCRIPTION OF EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram of an electronic musical instrument employing the vibrato generator of the present invention.

(101) is the Sa section (KB), (102) is the operation section (TAB) consisting of a tone tablet switch, vibrato effect on/off switch, glide effect on/off switch, etc., and (103) is the central processing unit (CP).
(104) is a readable/writable storage device (random access memory called RAM), (105) is a C
A read-only storage device (read-only memory, called ROM) stores a program that determines the operation of P U (103), and (106) stores waveform sample data for musical tone synthesis and waveform interpolation. This is a ROM that stores control data, etc. (107) is R
a musical tone generator (10) that generates musical tones using waveform sample data and control data stored in the OM (1oe);
8) is a filter that removes sampling noise, (10
9) is an electroacoustic transducer.

Keyboard section (101), operation section (102), CPU (1
03), RAM (104), ROM (106) (1
06), the tone generator (107) is connected by a data bus, an address bus, and a control line. The method of coupling data buses, address buses, and control lines in this manner is a well-known method for configuring minicomputers and microcomputers. Eight to 16 data buses are used, and data is transmitted and received on these bus lines not in one direction but in multiple directions in a time-division manner. Multiple address buses, for example 16, are prepared, and normally the CPU (108) outputs the address code,
Other parts receive the address code. As the control line, a memory request line ('MRKO), an I10 write line (WR), etc. are normally used.

MRKQ indicates reading and writing memory, l0RQ
indicates that the contents of the input/output device (Ilo) are to be retrieved, RD indicates the timing of reading data from the memory or device 10, and 11 indicates the timing of writing data to the memory or Ilo.

An example of a microprocessor using such a control line is the microprocessor 280 manufactured by Zilog.

Next, the operation of the electronic musical instrument shown in FIG. 1 will be described.

The keyboard section (IQl) is configured to divide a plurality of key switches into a plurality of groups and to be able to collectively send the on/off states of the key switches in the group to the data bus. For example, in the case of a 61-key keyboard, each 6-key (half-octave)
Divide into 11 groups, 0 group and 1 key group, and assign one address code to each group. An address code indicating one of the above groups arrives on the address line, and a signal X O
When RQ and signal RD are applied, the keyboard section (1o1) decodes the address code and sends 6 bits (t) or 1 bit data indicating on/off of the key switch in the corresponding group to the data bus. Output to. These can be constructed using decoders, bus drivers and some gate circuits. Of the operation section (1o2), the tablet switch can have the same configuration as the keyboard section (1o1).

The OPU (1oa) reads the instruction code from the address of the ROM (105) that corresponds to the code of the program counter inside it, decodes it, and performs arithmetic operations, logical operations, reading and writing data, and reading and writing of the program counter. Performs tasks such as jumping instructions due to content changes. The procedures for these operations are written in ROM (1OS). First, the CPU (103) is a ROM
(105) reads the command to import the data of the keyboard section (1o1), and turns on/off each weight of the keyboard section (1o1).
A code indicating OFF is imported for each group. Then, the pressed key code is assigned to a finite channel of the musical tone generator (107), and musical tone generation data corresponding to the key code is sent out.

Next, the CPU (103) sequentially transfers a group of instructions to read data from the operation unit (102) to the ROM (1o6).
and decode these to create an address code and control corresponding to the operation unit (102)'j)IORQ
and FID, outputs a code representing the state of the switch of the operation unit (102) to the data bus, and
(1o3). Based on the data read into the CPU (i 03 ), it selects a tone and generates predetermined effect control data, and sends the tone selection data to the ROM (1oe) and the effect control data to the musical tone generator (107). . Note that the key code being pressed is sent to the musical tone generator (1
The method of allocating channels to a limited number of channels (07) itself is known as a generator assigner function.

Based on the musical tone generation data supplied from the CPU (103) 75, the musical tone generating section (1o7) fetches predetermined waveform sample data and control data from the musical tone synthesis data ROM (106) and performs waveform interpolation processing. A musical sound waveform is generated and passed through a filter (108) to an electroacoustic transducer (
109') to generate musical tones.

FIG. 2 shows a time chart when data is supplied from the CPU (1os) to the tone generator (107).

A '110 port address is supplied to the address bus, and musical tone generation data, effect control data, etc. are supplied to the data bus. Then, at the timing when the control signals IORQ and WR change from logic low level (hereinafter abbreviated as "0") to logic high level (hereinafter abbreviated as "1"), step 10
Latch the contents of the data bus into the channel specified by the port address.

Next, various types of data supplied to the musical tone generating section (107) will be explained.

Table 1 shows the I10 boat address and various data.The I10 port address is displayed as 16. I10 boat address (00)16 to (07)16
The data corresponding to the musical tone generation data can be generated for 8 channels, that is, for 8 tones. The I10 port address (08) He is sustain data that specifies the attenuation characteristic of the envelope signal. The I10 port address (09)16 is damper data that becomes valid when the envelope characteristic is piano type, and, like the sustain data, specifies the attenuation characteristic of the envelope signal. Address (0m) 16 is pitch control data, which is used to shift the note clock from its normal value. I10 port address (OB)1
Reference numeral 6 indicates effect control data, which is composed of a Hi:Brato on/off signal, a glide on/off signal, and the like.

I10 port address (OC) 16 is vibrato select data, which selects one from among multiple vibrato data.
This data is used to specify one vibrato data.

The I10 port address (OD) 16 is vibrato speed data in Tables 1, 2, and 3, and is data that specifies the vibrato frequency.

Table 2 shows the composition of the musical tone generation data. D3 from pit position no. is note clock designation data that designates the scale frequency. Pit positions D4 to D6 are waveform sample number designation data that designate the sound generation range. Pit position D
Reference numeral 7 indicates a key on/off signal accompanying the on/off operation of the key switch, which is "0" when off and "1" when on.

Table 3 shows the code contents of the waveform sample number designation data SDO-8D2 and the number of samples in one cycle of the waveform designated by the code. The waveform sample number specification data 5D is (oo
o) From 2 to (111) 2 i , (D8f!

Table 4 shows note clock designation data NDo-, -ND3.
This shows the relationship between the contents of the chord represented by and the specified scale specified by that chord.

On the Chikud table, the address of the control day I is written on the 10th page. 4th
The off position Do is the vibrato on/off signal VIB, which is "0" when the vibrato on/off switch in the operating section (102) is off, and "1" when it is on.

Bit position Dl is delay vibrato on/off signal D
VIB is a delay vibrato effect control signal, which is "0" when the delay vibrato on/off switch in the operation unit (1o2) is off, and "1" when it is on.

Bit position D2 is the glide on/off signal GL, which is “0” when the glide switch in the operation unit (102) is off;
It becomes “1” when it is on.

Bit position D3 is organ type/piano type designation signal OPS
This specifies the envelope characteristics, and is "0" for an organ type and "1" for a piano type.

Bit position D4 is damper on/off No. 414 DMP,
This is valid only when the envelope characteristic is piano type, and is "0" when the damper is off and "1" when it is on.

FIG. 3 is a configuration diagram of the musical tone generator (1,07). .

Table 6 In Figure 3, (3o1) is the main oscillator, (302) is the sequencer that controls the operation contents of the musical tone generator (107), and (303) is the main oscillator that controls the various data supplied from the OPU (1os). An input register section for latching, (304) a timer, (305) a comparison register section, (3oe) a frequency data processor (hereinafter abbreviated as FDP) that generates frequency data corresponding to the frequency to be generated, (307)
) is a waveform data processor (hereinafter referred to as WDP) that performs waveform interpolation processing, and (308) is a musical tone synthesis data ROM.
(1o6) is a data read processor (hereinafter abbreviated as DRP) that reads waveform sample data, control data, etc. from (1o6), (309) is a read pulse forming unit that generates a pulse signal with a predetermined pulse width, and (310) is W D P(
307).

(311) is a digital/analog converter (hereinafter abbreviated as DA (+)) that converts a digital signal to analog i, (312) is a 1 Consists of two analog switches and one capacitor per channel.
Analog buffer memory section that holds analog signals (
313) is an integrator.

Here, the waveform interpolation method executed by the WDP (207) will be explained.

As a waveform interpolation method, 1-4-1 (i==o, 1.2...
, l-1), one cycle of the musical sound wave repeats M times, and the waveform samples f(Xi, n) and f (X
An attempt is made to approximate the virtual sample value △ f (Xi, m, n) that exists between i, +t, n) by virtually calculating the waveform sample value of the virtual sample point using an interpolation operation. It is something. The interpolation formula is shown below.

f(Xi, m, n) = (7(Xi+t, n) - f(X
i, n)) i is the sample position extracted by division,
This is the waveform number. (i=o, 1.2, -, I
-1) m represents a position in the middle of a repeating transition from waveform number i to 1+1 M times.

(m=Q, 1.2.--., M-1) n is a sample position obtained by dividing one cycle of the musical sound waveform into N, and is a waveform sample NAND.

(n=0.1.2, ---, N-1) In addition, W D P (207), D RP (20B
) Regarding the peripheral operations, see Japanese Patent Application No. 57-231482.
This is described in detail in ``Musical Sound Generator''.

In the above configuration, (304) (305) (306) (
310) constitutes a note clock generation section that determines the tone scale, and based on its output signal, the data reading section DRP (308) generates musical tone synthesis data ROM (
106).

In addition, an input register section (308), a comparison register section (308), and a comparison register section (308)
05), F D P (soe), w n P (30
7), DRP (308), calculation request flag generation unit (31
0), the procedure for processing is determined by the sequencer (302).

When musical tone generation data is supplied from cP U (103) to a predetermined channel, for example channel 1, at a predetermined timing determined by the sequencer (302), from the input register section (303) to F D P (306), W
Tone generation data is supplied to D P (307) and D RP (308). Then, the DRP (308) reads waveform sample data and control data from the musical tone synthesis data ROM (106). Then, let t (xi, n) shown in equation (1) be data WDI, and f (
Xi+x, n) as data, W D P (307
). Furthermore, the numerator term (Nm+n) of the interpolation coefficient shown in equation (1) based on the read control data is supplied to W D P (307) as data MLP. Furthermore, when the final waveform data is reached, a WEF signal indicating the final waveform data is supplied to W D P (307).

w DP (307) uses data WDI, WDII, and MLP supplied from D RP (308),
It performs waveform calculation processing according to equation (1) and supplies it to the DAC (311). And in DA(i(311)), WDP
The digital signal supplied from (307) is converted into an analog signal, and is supplied as an analog signal to the analog buffer memory section (312), where the capacitor charge corresponding to channel 1 is stored.

On the other hand, in the F D P (306), the input register section (
Frequency data is generated based on the musical tone generation data supplied from the section 303), and is supplied to the register corresponding to channel 1 of the comparison register section (305). Then, the data and timer (305) are supplied to the comparison register (305).
04), and if a match is detected, a matching pulse is read out and supplied to the pulse forming section (309) and calculation request flag generating section (310).

Then, the read pulse forming section (309) generates a read signal force 1 having a predetermined pulse width, and supplies it to the analog buffer memory section (312). The charge stored in the capacitor corresponding to channel 1 in the analog buffer memory section (312) flows into the integrator (313) by the read signal.

The calculation request flag generation unit (310) generates eight samples of the next waveform, that is, a virtual sample point f (Xi, m, n+
t) generates and holds a computation request flag.

Then, when the processing timing reaches channel 1 again, the calculation request flag has been generated, so waveform interpolation processing is performed in the same way as described above, and the analog buffer memory section (3
Charge is stored in the capacitor in 12). Thereafter, waveform interpolation processing is performed in response to the calculation request flag, and a musical tone waveform is generated.

Note that the charge stored in the capacitor is Nohe Xi, m, n-
1) and the waveform sample value f (Xi, in
, n). And the integrator (313)
The waveform sample value fACXi, m, obtained this time by
n) will be restored. The operations around the analog buffer memory section (312) and the integrator (313) are described in Japanese Patent Application No. 57-126413R Waveform Reading Apparatus.

FIG. 4 is a block diagram of a specific example of the sequencer (302). In the figure, (401) is the two-phase clock signal φ1
and a two-phase lock generation unit (402
) is a hexadecimal counter that determines the operation sequence for each channel, (403) is a counter that generates a channel code that is currently being processed, and (404) is a FIOM in which the operation procedure is stored.

(405) is a decoder. Figure 5 shows the sequencer (3
02) is shown.

A master clock (MCI) signal is supplied from the main oscillator (301) to the two-phase lock generation section (401).

The two-phase lock generating section (401) generates the two-phase lock signal φ1. as shown in FIG. Generates φ2.

Signal φ1 is supplied to the decimal counter (402) and the counter (,4
03).

The hexadecimal counter (402) has a 4-bit configuration, and count amplification processing is performed at the timing when the signal φ1 changes from "0" to "1", and the output signal becomes (1111
)2, and when you next count up (olol
)2 cents. As a result, the decimal counter (40
The output signal of 2) is in 11 states, i.e. (olol)2
~(1111)2. This is used as a command step signal.

The counter (403) has a 3-bit configuration, with 11
Count amplification processing is performed every time the output signal of the counter (40,2) changes from (1111)2 to (olol)2. As a result, the output signal of the counter (403) becomes a state of 8, that is, (ooo)2 to (11' - 2°). This is used as a channel code.

The ROM (404) reads out an instruction code based on the instruction step signal supplied from the hexadecimal counter (402) and supplies it to the decoder (4OS). Decoder (4os
) decodes the instruction code supplied from the ROM (404) and supplies processing control signals to each section.

, as a result, the calculation time per channel is 2.76 μs
Therefore, each calculation process is performed in 11 instruction steps. And 22. ) The calculation timing is repeated every 1B.

FIG. 6 shows a configuration diagram of a specific example of the analog buffer sofa memory section (312). In the figure, (eol) is the input terminal, (60
2) is an output terminal, (603) to (60s) are analog switches, and 01 to C3 are capacitors.

Signals AW1 to AW8 supplied to the gate inputs of analog switches (603) (606) (607) are WDP
It is supplied from 307. There are still analog switches (
Signals AR1 to AR8 supplied to the gate inputs of 604), 606, and 608 are read pulse generators (3
09).

The analog signal converted by the DAC (311) is applied to the input terminal (601) and is applied to the analog switch (603) (e
ots ) (607). If the data corresponds to channel 1, the analog switch (6
03) is turned on, and the charge corresponding to the analog signal applied to the input terminal (6o1) is stored in the capacitor a.

Thereafter, when the read pulse R1 corresponding to channel 1 is supplied from the read pulse generator (309) to the gate input of the analog switch (604), the capacitor C
The charge stored in the integrator (313) is supplied to the integrator (313) via the output terminal (602).

Analog switches (603) (605) (607) are W
Since it is synchronized with the operation timing of D P (307), multiple units are not turned on at the same time. Since the analog switches (604, 606, and 608) are turned on in synchronization with the musical scale frequency, a plurality of them can be turned on at the same time.

This is a running chart. FIG. 7 shows the timing for four channels.

Explanation of Abbreviations in the Figure ORF is a calculation request signal for each channel. The request start time is synchronized with the coincidence signal supplied from the comparison register section (305). That is, it is synchronized with the scale frequency, and for example, in the C scale, it occurs every 59.74 μs.

cLc indicates waveform calculation timing.

DAC indicates the timing for storing charge in the capacitor in the analog backup memory (312) via the DAC (sll).

OTC is the timing at which the charge stored in the capacitor in the analog backup memory (312) is supplied to the integrator (313), and is generated in synchronization with the scale frequency, similar to CRF.

The time chart of channel 1 will be explained.

The calculation timing corresponding to channel 1 is determined by the sequencer (3
02), and as shown in the figure, calculation timing occurs every 22 μs.

(2) Signal CRF1 is generated in the middle of channel code 1. Waveform interpolation processing and frequency data update are not performed at the timing when the signal 0RF1 is generated, and the signal 0TO1 is generated at the same time, and the charge of the capacitor C1 in the analog buffer memory (312) is transferred to the integrator ( 313). The pulse width of the signal OTC is 2
It is about female S.

(2) When the channel code becomes 1 again, reading processing of waveform sample data, waveform interpolation processing, frequency data updating processing, etc. are performed.

■...When the arithmetic processing of channel 1 is completed, the signal DA
C1 is generated and connected to capacitor C via DAC (311).
Charge is stored in 1.

O...When the arithmetic processing of channel 1 is completed, the signal CR
Reset F1 and cancel the calculation request.

■...Similar to the above ■, at the timing when the signal CRF1 is generated again, at the timing of the above ■, the capacitor C
The charge stored at 1 is supplied to an integrator (313).

From then on, as described above, each time the signal (3RF) is generated,
One temporary phase waveform sample value calculation process and frequency data update process are performed, and the waveform calculation result is sent to an integrator (31s
).

The relationship between the calculation cycle and the scale period is good as long as the calculation timing for the same channel can be performed twice within the minimum scale period and the calculation result can be stored in a capacitor in the analog buffer memory section (312).

That is, it is sufficient to provide calculation timings corresponding to 10 channels within the minimum scale period in consideration of vibrato, glide, etc.

Description of how to generate pitches Regarding notes, a clock signal corresponding to a 12-tone scale is generated. Regarding octave relationships, pitches related to octaves are generated by changing the number of samples in one period of the musical sound waveform stored in the musical tone synthesis data ROM (106).

If the cO' sound (32,708Hz) is 612 samples, the note clock signal is 32.708H2X512
Sample #16.74 KHz. Table 6 shows the note clock frequency, and Table 7 shows the number of waveform samples and the octave relationship.

Explanation of the method for generating scale periods FIG. 8 shows the transition of frequency data supplied from the F D P (306) to the comparison register section (305).

The timer (304) consists of a 10-pin binary counter, and the output status is expressed in hexadecimal as (ooo
)16 to (3FF)16, count amplification is performed sequentially from (3FF)16 to (ooo)16 again,
(ooo) 16 to (3”) 16 is the main oscillator (301
) is repeated based on the signal MCI supplied from ).

That is, the repetition period TR of the timer (304) is as shown in the following equation.

Table 6 fMOK=8. OO096MHz Table 7 = 210 x '--- 8, To OO096MH2 = 127.98, 1ill The output data transition state of the timer (304) is described as the timer output data in FIG.

The scale period is generated by comparing the output signal of the timer (304) with the frequency data supplied from the FDP (306), and if a match is detected, a matching pulse is sent from the comparison register section (305). . The generation cycle of the matching pulse becomes the scale cycle of the scale to be sounded.

As shown in FIG. 8, by updating the frequency data, a synchronized cross signal can be generated.

That is, the arithmetic processing shown in the following formula is performed by F and DP.

(soe).

NFD=MOD(OFD-1-FD, TD, ax)”
"" (3) NFD is new frequency data.

OFD is frequency data before update.

FD is scale data determined by the generated scale. ' TDmaX is the number of output states of the timer (304). In this example, TDmax is 216, that is, 1024
It is.

Table 8 shows scale data PD corresponding to the 12-tone scale.

FIG. 9 is a block diagram of a specific example of FDP (306). In FIG. 9, (sol) is a cent scale data generation unit (hereinafter referred to as CPD generation path) that generates scale data expressed in cent scale (referred to as CtPD), and is composed of a ROM that stores cent scale data. Note clock designation data (ND), waveform sample number designation data (SD), and organ type/piano type designation signal (OP)
S) Selectively generates CPD based on K. (902) is a pitch control data gate that selects pitch control data; (903) is a vibrato signal generator that generates a vibrato signal; (904) is a vibrato signal generator that generates a vibrato signal;
is a glide signal generator (905) that generates a glide signal.
) is an exponential converter, which converts a frequency value expressed in cents scale into frequency data that is directly proportional to the frequency.

Table 8 Numerical representation is in decimal.

(906) is the arithmetic unit, (907) is the lunch (denoted as MU), (908) is the latch (denoted as BL), (909)
is an adder (assumed to be F), (910) is a buffer, (9
11) is a gate. (912) (913) (914
) is the pass line, (912) is FA Babasu (913)
is the FB bus (914) is the FC bus.

Note that the pitch control data cpcn, vibrato data CVD, and glide data CGD are also expressed in cent scale.

Structure of various data Cent pitch data (CPD) It is composed of 11 pits, with the upper 4 bits representing 12-tone equal temperament, and the lower 7 pins representing each point of the chromatic scale divided into 128 equal parts.

Pinch control data (CPCD), vibrato data (cvn), and crite data (CHD) each have an 8-bit configuration, using 2's complement representation, and 12 chromatic scales.
It has a resolution divided into eight equal parts. It also represents positive and negative pitch control components, vibrato components, and glide components.

Description of Vibrato Signal Generating Section (903) FIG. 10 shows a configuration diagram of a specific example of the vibrato signal generating section (903). In the figure, '(1oo1) is a vibrato ROM that stores a plurality of vibrato data cvn, (1002) is a vibrato address register that stores address data for reading out the vibrato data stored in the vibrato ROM (1oo1), (1003) is a gate used for delay vibrato young fruit, (1004) is a gate that supplies the output signal (vibrato data CVD) of the shifter (1003) to the FB bus by signal RDCVD;
(1006) is the operating condition of the vibrato signal generating section (903) based on the tail signal qKD, 4i%VIB, signal DVIB supplied from the input register section (303) and the signal CHC supplied from the sequencer (302). The condition setting section (1oo6) that sets the register (1002
), a selector that selects data to be stored in (100
7) is a gate, (1oo8) is an AND gate, (100
9) is a carry detection unit that detects a carry in the vibrato data p (cvn).

Principle of vibrato signal generation FIG. 11 is a data map diagram showing the contents of the vibrato ROM (1o01). One vibrato data memory has a structure of 2048 words with 8 bits per word, and stores data representing a vibrato waveform. The vibrato ROM (1o01) is composed of 16 such vibrato data memories, and one vibrato data memory is selected by the lower 4 bits of the vibrato select data VBD supplied from the input register section (303). Ru.

Normally, 14-bit vibrato address data is supplied from the FC bus to the register (1002) via the selector (1ooe). Note that the lower 11 pits of the 14-bit vibrato address data are supplied to the vibrato ROM (10o1) as address data, and the upper 3 bits are supplied as shift data to the thick (10o1).
03).

(-1002) Vibrato data is supplied to the FB bus via (1004) according to the address supplied from (-1002).

On the other hand, the vibrato address data of the 14-pinto configuration is directly supplied to the FB bus via the FB bus (1007), incremented by 1 in the arithmetic unit (906), and then supplied to the FC bus again. By repeating this, the vibrato address data becomes 1
Progress step by step.

Therefore, the vibrato address data supplied from the FC bus is added to the vibrato ROM (1001) as a read address and is transferred from the FC bus to the FB bus for the purpose of incrementing the vibrato address itself.

The selector (10oe) is Vipler) ROM (1001
) and the shifter (1003) to set the initial value of the vibrato address data. In other words, the selector (10o6) normally selects the vibrato address data supplied from the FC bus, and the vibrato address data is I18ru. When the address data corresponding to the lower 11 bits of the vibrato address data overflows, a flag is set in the carry detection section (1oo9), and an initial value selection signal is sent to the selector (10o6).
Select the initial value TBS (vibrato speed data) supplied from . After that, the selector (1006) selects the FC
The vibrato address data supplied from the bus is selected and normal step processing is performed.

Therefore, the address data, which is the lower 11 pits of the vibrato address data, varies from the initial value TBS to the final value (
2048) 10.

The method of setting the vibrato frequency will be explained below.

Note that the maximum R value of the address (2
048) The number of addresses up to 1o will be called the address length.

The reason why the initial value of the vibrato address data is referred to as VBS (vibrato speed data) is that the initial decay value determines the frequency of the vibrato. In other words, since the time required for one step of vibrato address data is constant, the time required for one cycle of vibrato is determined by the value of the address length. In other words,
The address length value determines the vibrato frequency.

FIG. 12 is an example of vibrato data for one cycle stored in the vibrato ROM (1001).

Note that the horizontal axis represents addresses, and the vertical axis represents the size of vibrato data.

In this case, the vibrato speed data (TBS) is (
□oo )16= (o) 10 to (2A O)1
By changing the address length between 6=(672)10, the address length changes from 2048 to 13764, so 48.
A change in vibrato frequency of 8% is obtained.

However, as the vibrato frequency changes, the vibrato waveform also changes. Also vibrato speed data (VB
S) The initial value of the tsumashi address is (2mu0)15=67
If it exceeds 2, the data corresponding to the initial value of the address and the data corresponding to the final value will not match, causing discontinuity in the vibrato waveform. Therefore, the maximum value of the vibrato speed data (TBS) is @It is necessary to keep it within a range that does not cause problems on the road.

A method for selecting vibrato data corresponding to vibrato speed data VBS will be described below.

FIG. 13 shows an example of vibrato data stored in the vibrato ROM (1oo1), and the data in FIG. It is assumed that the data shown in FIG. 13(b) is stored in the 20th section. The horizontal axis is the address value expressed in decimal notation.
The vertical axis represents the magnitude of vibrato data. 13th
In the figure, data in (a) is vibrato data corresponding to vibrato speed data VBS = (ooO)16 and address length = 2048, and data in (b) is vibrato data corresponding to VH5 =
(1oo)16 = (256)to address length ==1
This is vibrato data corresponding to 792. At this time C
PU (103) generates vibrato select data VBD=(oo)16 when V B 8 = (000)16. T
When BS=(1oo)16, vs D= (01)t
Control is performed so that e. Then v B S =
(ooo)16 and e can also add a sine wave vibrato when VBS=(1oo)16.

Using this method, regardless of the vibrato frequency,
A constant vibrato waveform is obtained, and no discontinuity occurs in the vibrato waveform.

The relationship between the vibrato speed data vBs and the vibrato frequency will be specifically shown below.

If the vibrato data is read out at the calculation timing of channel code 1 and once every four times, the readout cycle will be 88/Z8.

V B +9 = (000)16 When o, the atto L/s length is 2o48, so fr) = 1/(22fi8X4X2048) = 5.55
When H2VB 5 = (100) 16 = (256) to, the address length is 1792, so f 1 = 1/ (22fi8 X4 X 1372
) ==5.34 Hz.

In this embodiment, the vibrato frequency is changed by changing the initial value of the vibrato address, but the final value of the address, the initial value,
A similar effect can be obtained by controlling both final values.

On the other hand, SHICK (10o3) controls the amplitude of vibrato data CvD supplied from the Vibrato ROM (1003) based on shift data. Shift data V8FD and shifter (1003) output data 08
The relationship with FD is as follows.

V 8 F D = (000)2 =-O8F D=
(OO)16, VSFD=(001)2. ,．． 05FD
=(CVD/64), VSFD=(010)2-, .
08FD=(CVD/1o),..., V8FD
=(110)2-O8FD=(CVD/2), vsFD
==(111)2-O8FD=(cvn) The condition setting section (1006) sets the following operating conditions.

Vibrato off This is the case when the vibrato on/off signal VZB is “0”, and the output of the selector (1oo6) is forced to always (oo).
16. Then, the shift data of thick (1003) will always be (000)2. As a result, chic (
The output data of 1003) is (00)16.

That is, the vibrato data CVD is always (oo)ts
becomes.

Vibrato on/vibrato on/off signal 49VIB is “1” and signal DV
When IB is "0", the vibrato is on. The address data stored in the register (1002) is passed through the gate (10o6) to the gate (1o07) and the chic (
1oo3). Note that the upper 3 bits of the address data, that is, the shift data, are forced (111).
Set it to 2. Then, the output (vibrato data cvn) of the Pippler ROM (1oo1) is supplied to the input of the gate (1004).

When the f-era vibrato vibrato on/off signal VIB and the delay vibrato on/off signal DVIB are "1", a delay vibrato state is entered. When all the key on/off signals KD of the 8 channels are turned off and any one of the key on/off signals KD is turned on, the address data is changed to (0).
The gate (100e) is controlled to set it to 00)16. Then, in Schick (1003), the amplitude control of vibrato data CvD (o, CVD/1o, CVD/1o, CVD/
1 o.

OVD/s, OVD/a, CVD/2, 0VD). Then, when the shift data becomes (111)2, the shift data is forcibly set to (111)2 as in the vibrato-on state.

The explanations of the symbols listed in Table 9 are as follows.

MUL latches the data supplied to the FM bus at the falling edge of signal φ2.

BL is an instruction to clear the data supplied by the FB bus, and the signal 0RAL is to clear the lunch timing L with the signal φ2 of '1'.

Mu DD1 is an instruction to add "1" to the carry manpower of FA (909).

TCA is an instruction to supply the result of arithmetic processing in FA (909) to FA bus.

RDCPD is an instruction for supplying cent pinch data CP D to the digital path generated by the CPD generation unit (901).

RDCP (3D is pitch control gate (902
) command to open the gate of FB bus pitch control data cpcn.

RDCVD is an instruction to supply vibrato data CVD generated by the vibrato signal generation section (903) to the FB bus.

RDOGD is a command for supplying glide data CGD generated by the glide signal generating section (904) to the FB bus.

R1) RX PHIQ% polish kB (cang) -
71” Fishing 1 - Order to supply FA Babasu with KXP (OPD).

RDΔKIP is Δ converted in the index converter (905)
K I P (OP D) woF J3 hash iC supply command.

RDFD is an instruction to read the surrounding frequency data OFD from the comparison register section (305) and supply it to the FB bus.

RDVAD is an instruction to supply the contents of the vibrato address register (1002) in the vibrato signal generator (903) to the FB bus.

RDCAD is an instruction for supplying glide address data from the glide signal generation unit (904) to the FB bus.

WRVAD is an instruction to write the result calculated by FA (909) to the vibrato address register (1002) in the vibrato signal generating section (903) at the rising edge of the signal φ2.

WRCAD is an instruction to write the result calculated by FA (eoe) to the glide signal generator (904) at the rising edge of the signal φ2.

WRKI P is an instruction to write the result calculated by FA (909) to the exponent converter (90B) at the rising edge of signal φ2.

WRFD is an instruction to write the result calculated by FA (909) to the comparison register section (305) at the rising edge of confidence φ2.

It should be noted that the 11 states at and 9th states occurring in the decimal counter (402) in the sequencer (302) are
This corresponds to command Step 11 shown in the table.

Vibrato address footpath processing instruction Step 1: Vibrato address register (100
2) The address data stored in latch BL (90
8).

Then, in instruction step 2, +1 is added to the vibrato address data vAD, and the added result is stored in the vibrato address register (102) again.

As described in detail, the vibrato adding device of the present invention changes the vibrato frequency by changing the read address length of the dibrato data memory and selecting the vibrato data memory corresponding to the address length. Therefore, a vibrato waveform of any frequency and any shape can be selected with a simple configuration.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an electronic musical instrument that employs the vibrato adding device of the present invention, FIG. 2 is a time chart diagram when data is supplied from the CPU (103) to the musical tone generator (107), and FIG. Configuration diagram of the musical tone generator (107), 4th
The figure is a block diagram of a specific example of the sequencer (302), and FIG. 6 is an operation time chart of the sequencer (302).
Fig. 6 is a configuration diagram of a concrete example of the analog sofa memory section (312), and Fig. 7 is an internal operation time chart of the musical tone generating section (107). FIG. 9 is a diagram showing the configuration of a specific example of y D P (306), and FIG.
) - A configuration diagram showing a specific example, Fig. 11 is a vibrato RO
FIG. 12 is a diagram showing an example of vibrato data, and FIG. 13 is a diagram showing an example of vibrato data corresponding to vibrato speed. (1o1)...Keyboard section, (602)...
Operation unit, (103)...Central processing unit, (10
4)...RAM. (1o6)...ROM, (106)...
・Musical tone synthesis data ROM, (107)...Musical tone generator, (301)...Main oscillator, (302)...
... Sequencer, (303) ... Input register section, (304) ... Timer, (305) ...
... Comparison register section, (306) ... Frequency data processor, (307) ... Waveform data processor, (308) ... Data read processor, (309) ... Read pulse forming section,
(310)...Calculation request flag generation unit, (31
1)...DACl (312)...Analog buffer memory section, (313')...Integrator, (901)...CPD generation section, ( 902)
...Pitch control data gate, (90
3)...Vibrato signal generator, (eo4)...
... Glide signal generation section, (905) ...
Exponent converter, (906)... Arithmetic unit, (100
1)...Vibrato ROM, (1006)--
-...Selector. Name of agent: Patent attorney Toshio Nakao and 1 other person No. 1
Figure 1s 2 Figure 9 ° Figure 1.0 Figure 03

Claims (1)

[Claims] a plurality of vibrato data memories that store a plurality of types of frequency modulation data; an address generator that generates addresses for the vibrato data memories; and a vibrato device that selects one vibrato data memory from the plurality of vibrato data memories. a data selection section; a note clock generation device that frequency-modulates a musical tone signal using the output data of the vibrato data memory; and an address length control section that controls the address length of the address generation section; A vibrato waveform of any frequency and any shape can be generated by controlling the address length and selecting the vibrato data memory corresponding to the address length by the vibrato data select section. A vibrato adding device.