JPS6032365A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To perform a complete electric isolation between bonding pads by providing the bonding pads on a portion that a buffer layer is not formed on a semi-insulating substrate, and connecting the pads to electrodes. CONSTITUTION:An active layer 3 and a buffer layer 2 remain insularly, and the surface is wet etched until the outside reaches a semi-insulating GaAs substrate 1. For example, AuGe-Ni-Au is used for the ohmic electrodes of source, 5, 6 and drain, a gate is formed of aluminum, and bonding pads 7, 8, 9, 10, 11 of the electrodes are wired. Thus, since the bonding pads are provided on the substrate 1 which show high resistivity higher by more than hundred times than the layer 2 and sufficiently high resistance as an isolating resistance, the resistances between the bonding pads increase, and the leakage of the signal in a semiconductor MES.FET integrated circuit is improved, and distortion characteristic is improved.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to semiconductor multiplication circuits, particularly compound semiconductor Schottky junction gate type FET integrated circuits such as GaAs.

Conventional structure and its problems GaAs-FET is an FE with excellent high frequency characteristics.
It is attracting attention as T. In recent years, attention has been paid to its multi-sided La stability and high yield GQ properties, and QaAs Schottky junction gate type FET integrated circuits [hereinafter referred to as GaAs-MES-
There are also 88 circuits called FET #416 circuit. When applied to practical circuits, especially tuners or reception front ends, important issues are not only the gain control width and input/output 1llvA degrees, but also the cross-modulation (distortion) characteristics when controlling the gain. Countermeasures for these important problems have not yet been reported for integrating QciAs-FE-r.

Generally, the most fundamental thing in a Te product circuit is the separation of individual elements. If this separation is incomplete, signals will leak, causing distortion, and the characteristics as a practical circuit will be significantly degraded. In a GaAs-MES-FET integrated circuit, a semi-insulating QaAS substrate can be used as the substrate, so conventionally the active layer 3 is mesa-etched as shown in FIG. By removing a portion of the active layer at the boundary of , individual F E, T are formed as islands on the surface of a high resistivity buffer layer 2 on a semi-insulating Ga AS substrate 1 . , 4, 5.6 are 1c gate, source, and drain formed on the active layer 3.

By the way, especially in the case of an integrated circuit, mutual interference of potentials may be observed even between FETs 1 to 1 of the FETs separated as described above. This is because the input resistance of the FET is high, several MΩ or more, so even if it is connected only by the high-resistance buffer layer 2 and the semi-insulating Ga AS substrate 1,
When two FETs are formed close to each other, the separation resistance between the closely placed FETs will be as large as the input resistance of the FET, resulting in
The input signal to the ET gate causes the other FET to
This is because the potential is affected and changes. Furthermore, such mutual interference between the gate potentials of the two FETs may occur due to leakage in the interlayer insulating film. Such mutual interference of gate potentials causes deterioration of distortion characteristics, signal leakage, etc., and becomes a problem when integrated circuits are formed.

Furthermore, the bonding pad is the one that has the greatest effect on such signal leakage. Conventionally, this bonding pad (not shown in FIG. 1) has been provided on the buffer layer 2, and since the area of the bonding pad is generally wider than the wiring etc., the mutual potentials through the buffer layer 2 are The interference is large and therefore leads to signal leakage.

OBJECTS OF THE INVENTION An object of the present invention is to provide a semiconductor integrated circuit that prevents signal leakage and improves distortion characteristics.

Structure of the Invention The semiconductor integrated circuit of the present invention includes a plurality of field effect transistors formed by forming an active layer on a semi-insulating substrate via a buffer layer and forming electrodes on the active layer. A bonding pad is provided on a portion of the insulating substrate where the buffer layer is not formed, each bonding pad is connected to the electrode, and complete electrical isolation between the bonding pads is achieved. do.

DESCRIPTION OF THE EMBODIMENTS An embodiment of the present invention will be described below with reference to the sectional view of FIG. 2 and the plan view of FIG. 3. Components similar to those in FIG. 1 are designated by the same reference numerals and their explanations will be omitted.

Here, a part of the buffer layer 2 on the semi-insulating QaAsl board 1 is removed, and the source pump of FETI, I [ padding pad 7, gate padding pad 8.9, and drain padding pad 10
．． 11 are provided.

12 represents the boundary of the seven buffer layers.

In the manufacturing process, first, the active layer 3 and buffer layer 2 are left in the form of islands, and the outer surfaces thereof are wet-etched until the semi-insulating Ga A5 substrate 1 is reached. The source 5.6 and drain ohmic electrodes were formed using Al1Ge-Ni-All, and the gate was formed using 8ρ. And then the bonding pad 7 of each electrode. 8. 9. 10.11
and did the wiring.

In this way, each bonding pad 7 is formed on the semi-insulating substrate 1, which has a resistivity more than two orders of magnitude higher than that of the buffer layer 2 and exhibits a sufficiently high resistance as a separation resistance.

8□9, 10.11 is provided, the resistance between the bonding pads increases, signal leakage in the semiconductor MES-FET integrated circuit is improved, and distortion characteristics are improved.

Furthermore, since the bonding pad is attached directly to the semi-insulated mountain board 1 of G A S '4f, rather than to an insulating material such as the bonding pad IS+O2, there is an advantage that the bonding pad is difficult to peel off during wire bonding. In addition, according to the above manufacturing method, since the buffer layer 2 is also etched, the difference in level is large, and the wiring may be disconnected due to this difference in level.
In order to prevent this, the thickness and thickness of the wiring to the bonding pads 7 to 11 should be made slightly larger. However, since this does not mean making the entire wiring of the circuit thicker, there is hardly any reduction in the degree of integration.

As a method for shaving this buffer layer 2, anisotropic web etching with side etching is more suitable than anisotropic dry etching. This is to create a slope on the etched side surface for wiring. In this way, disconnection of the wiring can be prevented.

As described in the detailed description of the invention, since the bonding pads are provided directly on the semi-insulating substrate in the semiconductor integrated circuit of the present invention, it is possible to prevent the potential from being affected by the resistance between the bonding pads. This makes it possible to improve distortion characteristics.

[Brief explanation of drawings]

FIG. 1 is an enlarged sectional view of a conventional GaAs-MES-FET, and FIGS. 2 and 3 are an enlarged sectional view and a plan view of an embodiment of the semiconductor integrated circuit of the present invention. 1. - Semi-insulating GaAS substrate, 2... buffer layer,
3... Active layer, 4... Gate electrode, 5... Source electrode, 6... Drain electrode, 7-11... Ponding pad, 12... Buffer layer boundary agent Morimoto Figure 2 depicting Yoshihiro

Claims (1)

[Claims] 1. An active layer is formed on a semi-insulating substrate via a buffer layer, and electrodes are formed on this active layer to constitute a plurality of field effect transistors, and the semi-insulating substrate A semiconductor integrated circuit in which bonding pads are provided in the portions on which the barrier layer is not formed, and each of the bonding pads and the electrodes are connected.