JPS623997B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an improvement in a method for manufacturing a field effect transistor with good high frequency characteristics.

Hereinafter, a method for manufacturing a gallium arsenide (GaAs) field effect transistor (hereinafter abbreviated as "GaAs-FET") will be described as an example.

1 to 3 are diagrams showing the main steps of a method for manufacturing an example of a conventional GaAs-FET.

First, as a first step, Figure 1A is a plan view, Figure 1B is a sectional view taken along line B-B in Figure 1A, and Figure 1C is a cross-sectional view taken along line C-C in Figure 1A. As shown in the cross-sectional view, an n-type film having an impurity concentration of about 3×10 ¹⁷ /cm ³ is formed on the main surface of a semi-insulating substrate 1 made of GaAs.
A GaAs layer 2 is formed, and a source electrode 3 and a drain electrode 4 are formed in parallel on a part of the surface of the n-type GaAs layer 2 at a predetermined distance from each other.

Next, as a second step, Fig. 2A is a plan view, Fig. 2B is a sectional view taken along line B-B of Fig. 2A, and Fig. 2C is a cross-sectional view taken along line C-C of Fig. 2A. As shown in the cross-sectional view, the n-type GaAs layer 2 is selectively etched to remove the region of the n-type GaAs layer 2 immediately below the source electrode 3 and drain electrode 4 and the region between these electrodes 3 and 4. and leave this as n-type GaAs
Layer 2a.

Next, as the third step, Figure 3A is a plan view, Figure 3B is a sectional view taken along the line B-B of Figure 3A, and Figure 3C is a cross-sectional view taken along the line C-C of Figure 3A. As shown in the cross-sectional view, on the surface of the n-type GaAs layer 2a in the region between the source electrode 3 and the drain electrode 4,
A gate electrode 5 having a predetermined gate length L is formed at a predetermined distance from these electrodes 3 and 4, and a gate electrode 5 having one end of an n-type GaAs layer 2a is formed on the main surface of the semi-insulating substrate 1. By forming the gate bonding pad 6 connected to the end of the gate electrode 5 through the end surface, this conventional method
The main part of GaAs-FET is obtained.

GaAs-FETs are generally used in small signal amplifiers, oscillators, etc. in the microwave region, so
It is necessary to improve high frequency characteristics. This GaAs
-The high frequency characteristics of FET are mainly influenced by the gate length L of the gate electrode and the gate-source capacitance _CGS .
This is improved by reducing the source-to-source capacitance _CGS .

However, in the conventional method, when the gate length L of the gate electrode 5 is shortened to improve high frequency characteristics, the connection between the gate electrode 5 and the gate bonding pad 6, that is, the end face of the n-type GaAs layer 2a is There was a problem in that wire breakage was likely to occur at the stepped portion, resulting in a decrease in product yield and reliability. In order to prevent such disconnection, as shown in the plan view of FIG. 4, a wide conductor width portion 5a is provided at the end of the gate electrode 5 to which the gate bonding pad 6 is connected. ,
Since the gate-source capacitance _CGS increases, there is a problem that high frequency characteristics deteriorate.

This invention was made in view of the above-mentioned problems, and even if a wide conductor width portion is provided at the end of the gate electrode to which the gate bonding pad is connected,
It is an object of the present invention to provide a method of manufacturing a field effect transistor with good high frequency characteristics and high reliability with a high yield by preventing the gate-source capacitance C _GS from increasing.

FIGS. 5 to 7 show GaAs according to an embodiment of the present invention.
- FIG. 3 is a diagram showing the main steps of the FET manufacturing method;

First, after passing through the first and second stages similar to the first and second stages of the conventional example shown in FIGS. 1 and 2, the third stage is shown in FIG. As shown in FIG. 5B, a cross-sectional view taken along line B-B in FIG. 5A, and FIG. 5C, a cross-sectional view taken along line C-C in FIG. A gate electrode 5 having a wide conductor width portion 5a at one end is formed on the surface of the region between the drain electrodes 4 at a predetermined distance from these electrodes 3 and 4, and is semi-insulating. Board 1
A gate bonding pad 6 is formed on the main surface of the gate electrode 5, one end of which is connected to the wide conductor portion 5a of the gate electrode 5 through the end surface of the n-type GaAs layer 2.

Next, as the fourth step, Fig. 6A is a plan view, Fig. 6B is a sectional view taken along line B-B of Fig. 6A, and Fig. 6C is a cross-sectional view taken along line C-C of Fig. 6A. As shown in the cross-sectional view, on the surface of the n-type GaAs layer 2a in the region between the source electrode 3 and the drain electrode 4,
It covers the surface of the gate electrode 5 except for the wide conductor width portion 5a and the portion between this portion 5a and the source electrode 3 and drain electrode 4, so as to reach from the surface of the source electrode 3 to the surface of the drain electrode 4. A resist film 7 is then formed.

Next, as the fifth step, Fig. 7A is a plan view, Fig. 7B is a sectional view taken along line B-B of Fig. 7A, and Fig. 7C is a cross-sectional view taken along line C-C of Fig. 7A. As shown in the cross-sectional view, selective etching was performed using the source electrode 3, the drain electrode 4, the gate electrode 5 including the wide conductor portion 5a, and the resist film 7 as masks.
In this embodiment, grooves 8 and 9 are formed in the n-type GaAs layer 2a between the wide conductor width portion 5a of the gate electrode 5 and the source electrode 3 and drain electrode 4, respectively. The main part of GaAs-FET is obtained by the method.

In the method of this embodiment, since the wide conductor width portion 5a is provided at the end of the gate electrode 5 to which the gate bonding pad 6 is connected, the gate length of the gate electrode 5 is shortened and the high frequency characteristics are improved. Even in the case where the gate electrode 5 and the gate bonding pad 6 are connected to each other, it is possible to prevent disconnection from occurring at the step portion of the end face of the n-type GaAs layer 2a, which improves the yield and reliability of the product. can be achieved. Furthermore, the n-type conductor between the wide conductor width portion 5a of the gate electrode 5 and the source electrode
Since the groove 8 is formed in the GaAs layer 2a, even if a wide conductor width portion 5a is provided at the end of the gate electrode 5 to which the gate bonding pad 6 is connected,
It is possible to prevent the gate-source capacitance C _GS from increasing, and high frequency characteristics are not deteriorated.

Although the method for manufacturing a GaAs-FET composed of an n-type GaAs layer formed on the main surface of a semi-insulating substrate has been described as an example, the present invention is not limited to this, and can be applied to other semiconductor layers. It can also be applied to a method of manufacturing a field effect transistor using.
The conductivity type of this semiconductor layer may be n-type or p-type.

As described above, according to the method for manufacturing a field effect transistor of the present invention, when forming a field effect transistor on a semiconductor layer formed on a semi-insulating substrate, The width of the connection portion between the gate electrode and the gate bonding pad formed on the semi-insulating substrate is increased at the portion across the stepped portion on the end surface of the semiconductor layer, and this widened portion is connected to the source electrode and Since grooves of a predetermined depth are formed in the portions of the semiconductor layer between the drain electrode and the drain electrode, even if the gate length of the gate electrode is shortened to improve high frequency characteristics, disconnection will not occur at the connection portion. It becomes possible to prevent this, and it is possible to improve product yield and reliability. Furthermore, by forming the groove, it is possible to prevent the gate-source capacitance C _GS from increasing even if the width of the connection portion is widened, thereby preventing deterioration of high frequency characteristics. There is no.

[Brief explanation of the drawing]

Figure 1A is a plan view showing the first step of the manufacturing method for an example of a conventional GaAs-FET, and Figure 1B is Figure 1A.
A cross-sectional view taken along line B-B of Figure 1C is Figure 1A
FIG. 2A is a plan view showing the second stage of the conventional manufacturing method, and FIG. 2B is a cross-sectional view taken along line C-C.
is a sectional view taken along line B-B in Figure 2A, Figure 2C
is a sectional view taken along line C-C in Figure 2A, Figure 3A
is a plan view showing the third step of the conventional manufacturing method, FIG. 3B is a sectional view taken along line B-B in FIG. 3A, and FIG. 3C is a cross-sectional view taken along line C-C in FIG. FIG. 4 is a plan view for explaining a method for preventing the occurrence of disconnection at the connection between the gate electrode and the gate bonding pad in the conventional example, and FIG. 5A is an embodiment of the present invention. A plan view showing the third step of the GaAs-FET manufacturing method, Figure 5B is the same as Figure 5A.
A cross-sectional view taken along line B-B of Figure 5C is Figure 5A
FIG. 6A is a plan view showing the fourth step of the manufacturing method of the above embodiment, and FIG. 6B is a cross-sectional view taken along line C-C of FIG.
is a sectional view taken along the line B-B in Figure 6A, Figure 6C
is a sectional view taken along line C-C in Figure 6A, Figure 7A
is a plan view showing the fifth step of the manufacturing method of the above embodiment, FIG. 7B is a sectional view taken along line B-B in FIG. 7A, and FIG. 7C is a cross-sectional view taken along line C-C in FIG. 7A. FIG. In the figure, 1 is a semi-insulating substrate, 2 is an n-type
GaAs layer (semiconductor layer), 3 is a source electrode, 4 is a drain electrode, 5 is a gate electrode, 5a is a gate electrode 5
6 is a gate bonding pad, 7 is a resist film, and 8 and 9 are grooves.
Note that the same reference numerals in the figures indicate the same or corresponding parts.

Claims (1)

[Claims] 1 Forming a semiconductor layer on the main surface of a semi-insulating substrate,
A step of forming a source electrode and a drain electrode parallel to each other at a predetermined distance on a part of the surface of the semiconductor layer, and selectively etching the semiconductor layer so as to be directly below the source electrode and the drain electrode of the semiconductor layer. and a region between these electrodes; a step of leaving a region between the source electrode and the drain electrode of the remaining semiconductor layer; A gate electrode having a wide conductor width is formed at an end of the semi-insulating substrate, and one end of the conductor of the gate electrode is formed on the principal surface of the semi-insulating substrate through the end surface of the remaining semiconductor layer. forming a gate bonding pad connected to the wide portion of the conductor on the surface of the region between the source electrode and the drain electrode of the remaining semiconductor layer;
forming a resist film covering the surface of the gate electrode except for the portion between this portion and the source electrode and the drain electrode so as to reach from the surface of the source electrode to the surface of the drain electrode; Then, selective etching is performed on the remaining semiconductor layer using the source electrode, the drain electrode, the gate electrode including the wide conductor width portion, and the resist film as a mask to remove the wide conductor width portion of the gate electrode. A method for manufacturing a field effect transistor comprising the step of forming grooves each having a predetermined depth in the remaining portions of the semiconductor layer between the source electrode and the drain electrode.