JPS603256B2 - synchronous circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a synchronization circuit for television video signals, and more particularly to a synchronization circuit for accurately synchronizing an accessory circuit such as a frame memory and an input video signal.

Generally, address generation circuits such as frame memories for television video signals need to use horizontal and vertical synchronization signals as reset signals, and a synchronization signal generation circuit is provided for this purpose.

In order to synchronize the synchronization signal generation circuit with the input video signal, the synchronization signal generation circuit is reset when the phase difference between the two exceeds an allowable value. FIG. 1 is a block diagram showing an example of a circuit for resetting a conventional synchronization signal generation circuit.

A video signal is extracted from a video amplification circuit of a television receiver, amplified by an amplifier circuit 1 biased to enable synchronization separation, and then a decoded synchronization signal is separated by a synchronization separation circuit 2. Further, horizontal and vertical synchronization signals are separated by a horizontal synchronization separation circuit 25 and a vertical synchronization separation circuit 26. On the other hand, synchronizing signals for the auxiliary circuits are generated by a horizontal synchronizing signal generating circuit 15 and a vertical synchronizing signal generating circuit 16 based on the clock signal of the clock generating circuit 14. The output of the horizontal synchronization signal generation circuit 15 and the output of the vertical synchronization signal generation circuit 16 are compared in phase with the synchronization signal of the input video signal by a horizontal synchronization phase detection circuit 27 and a vertical synchronization phase detection circuit 28. . If a phase shift is detected, the IJ set pulses P and Q reset the horizontal synchronizing signal generating circuit 15 and the vertical synchronizing signal generating circuit 16 to maintain synchronization. However, in the case of the circuit shown in FIG. 1, since the reset is performed immediately after the phase shift is detected, the reset position becomes random, which causes a problem in frame correlation in a one-frame memory or the like.

In view of the above-mentioned points, the present invention detects the presence or absence of a phase shift in a synchronization signal between an input video signal and an attached circuit such as a frame memory,
It is an object of the present invention to provide a synchronization circuit capable of accurately synchronizing an input video signal and an attached circuit by detecting in an even field and resetting a synchronization signal generating circuit in an odd field.

Hereinafter, the present invention will be described with reference to illustrated embodiments.

FIG. 2 is a block diagram showing a synchronous circuit according to one embodiment of the present invention, and FIGS. 3 and 4 are timing charts for explaining the operation. A video signal is extracted from the video amplification circuit of a television receiver, amplified by an amplifier circuit 1 biased to enable synchronization separation, and then processed by a synchronization separation circuit 2 to produce composite synchronization signals A and A' (A is an even field signal). , A' for odd fields).

The horizontal synchronization signal G is generated by a horizontal synchronization phase detection circuit 3, a low-pass filter (L, P, F) 4, a voltage controlled oscillator (V, C,
○) Detected by an AFC loop consisting of 5 and a frequency divider circuit 6. The vertical synchronizing signal B detected by the vertical synchronizing signal detection circuit 7 becomes a clear pulse of a frequency dividing circuit 9 used for field discrimination and one input of an AND circuit 8 for clock input control.

That is, the frequency dividing circuit 9 starts counting when the vertical synchronizing signal B falls, and stops counting when the vertical synchronizing signal B rises. Frequency dividing output ○ and E of frequency dividing circuit 9 (2.04 as clock)
When using 549MH2, a pulse F having a width of 1/27 and 1/ge output) to 1/r (where Hr is the period of the horizontal aircraft signal) is formed by one AND circuit, Since the horizontal synchronizing signal G is also supplied to the AND circuit 1, the output of the AND circuit 10 becomes like the sun, and it is detected that it is an even field. On the other hand, an AND circuit 12 generates a pulse having a phase difference of 1/2 Hr from the pulse F from the output of the imperter 11 which is the inverted frequency-divided output D and the output E. Since the horizontal synchronizing signal G is also supplied to the AND circuit 12, the output of the AND circuit 12 becomes like J, and an odd field is detected. If E is used as the clock input and day is used as the clear input of the JK flip-flop 13, a field index signal N (inverted output 1) which is inverted for each field is obtained.

A synchronizing signal for driving an attached circuit such as a frame memory is generated by a horizontal synchronizing signal generating circuit 15 and a vertical synchronizing signal generating circuit 16 from the clock of a clock generating circuit 14. This vertical synchronization signal is used as a clear pulse of the frequency divider circuit 18 and as an input of the AND circuit 17 for clock input control. Frequency divider circuit 18 operates in the same manner as frequency divider circuit 9 described above.

That is, the output of the frequency dividing circuit 18 has a waveform similar to that shown in FIGS. 3D and 3E. From the output of the frequency dividing circuit 18 having such a relationship, consider a pulse F in which 1/ has a width of r in the even field and a corresponding pulse in which 1/ has a width of r, and determine whether there is an H pulse among them. It is detected by the AND circuit 19. The AND circuit 19 outputs a pulse like K if the phase difference with the input video signal is within a permissible range. When this K pulse is used as the reset input of the RS flip-flop 20 and the J pulse is used as the set input, the Q output becomes L.

Therefore, a pulse is output to the output M of the AND circuit 21 only when there is a phase shift greater than the allowable limit in an even field. In addition, the allowable range of phase shift is the frequency divider circuit 1.
8 and AND circuit 19 can be freely selected. If this M pulse is used as the set input of the RS flip-flop 22 and the field index signal N is used as the reset input, the Q output becomes 0.

When the vertical synchronization reset circuit 23 and the horizontal synchronization reset circuit 24, which are triggered by the falling edge of this 0 pulse and use a monostable multi-channel, are operated, the even field in which the phase shift has been detected is switched to the next odd field. At the turn, set pulses such as P and Q are output. This reset pulse resets the horizontal synchronizing signal generating circuit 15 and the vertical synchronizing signal generating circuit 16.
With the above circuit configuration, when a phase shift with the input video signal is detected in the even field, the synchronization signal generation circuit is reset in the odd field, and the input video signal is always synchronized with the attached circuits such as frame memory. can be kept.

As described above, according to the present invention, the presence or absence of a phase shift between the synchronization signal between the input video signal and an attached circuit such as a frame memory is detected in the even field, and the synchronization signal generation circuit is reset in the odd field. By doing this, there is an advantage that the input video signal and the attached circuit can be accurately synchronized without damaging the frame correlation.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an example of a conventional synchronous circuit, FIG. 2 is a block diagram showing a synchronous circuit according to an embodiment of the present invention, and FIGS. 3 and 4 are the circuits shown in FIG. 3 is a timing chart showing the operation of FIG. DESCRIPTION OF SYMBOLS 1... Amplifier circuit, 2... Synchronous separation circuit, 3... Horizontal synchronous phase detection circuit, 6, 9, 18... Frequency divider circuit, 8, 1
0, 12, 17, 19, 21...AND circuit, 11...Inverter, 13...JK flip-flop, 14...Clock generation circuit, 15...Horizontal synchronization generation circuit, 16...Vertical synchronization generation circuit, 20, 22... RS flip flop,
23...Vertical synchronization reset circuit, 24...Horizontal synchronization reset circuit. Hair rod diagram 1 Figure 2 Figure 3

Claims (1)

[Claims] 1 detection means for separating and detecting horizontal and vertical synchronization signals from an input video signal; 1 gate signal, and generates a second gate signal having a phase shift of 1/2·Hr and a width of 1/2·Hr with respect to the first gate signal. means, taking an AND of the first gate signal and the horizontal synchronization signal and an AND of the second gate signal and the horizontal synchronization signal, and outputting an even number or odd field discrimination signal as each AND output. a second signal generation means for generating horizontal and vertical synchronization signals for an auxiliary circuit to be synchronized with the input video signal; a third signal generating means for generating a third gate signal having a width of 1/2·Hr corresponding to the first gate signal within a period;
a first flip-flop circuit that is reset by an AND output of the gate signal of the gate signal and the even field discrimination signal and is set by the odd field discrimination signal; and a first flip-flop circuit that is set by the odd field discrimination signal; a fourth signal generating means for generating a field index signal that is inverted for each field; and a fourth signal generating means for generating a field index signal that is inverted for each field; and performing an AND operation between the output of the first flip-flop circuit and the even field discrimination signal; a fifth signal generating means that outputs a pulse when a phase shift in an even field with respect to the output from the generating means exceeds a predetermined value; and the fifth signal generating means is reset by the output of the fifth signal generating means, and the field index signal a second flip-flop circuit, and means for resetting the horizontal and vertical synchronizing signal generating circuits in response to the output of the second flip-flop circuit.