JPS6035531A - Manufacture of semiconductor chip - Google Patents

Manufacture of semiconductor chip

Info

Publication number
JPS6035531A
JPS6035531A JP58144666A JP14466683A JPS6035531A JP S6035531 A JPS6035531 A JP S6035531A JP 58144666 A JP58144666 A JP 58144666A JP 14466683 A JP14466683 A JP 14466683A JP S6035531 A JPS6035531 A JP S6035531A
Authority
JP
Japan
Prior art keywords
resin
semiconductor
semiconductor chips
base substrate
semiconductor wafer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP58144666A
Other languages
Japanese (ja)
Other versions
JPH0342506B2 (en
Inventor
Hiroshi Tanabe
田辺 宏
Isao Shibata
柴田 勲夫
Takashi Okada
俊 岡田
Yoshinori Arao
荒尾 義範
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Oki Electric Industry Co Ltd
Original Assignee
Oki Electric Industry Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Oki Electric Industry Co Ltd filed Critical Oki Electric Industry Co Ltd
Priority to JP58144666A priority Critical patent/JPS6035531A/en
Publication of JPS6035531A publication Critical patent/JPS6035531A/en
Publication of JPH0342506B2 publication Critical patent/JPH0342506B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P54/00Cutting or separating of wafers, substrates or parts of devices

Landscapes

  • Dicing (AREA)

Abstract

PURPOSE:To improve the handling property of semiconductor chips as well as to contrive to reduce the working manhour and to upgrade the manufacturing efficiency by a method wherein the supply to B stage curing type resin to the semiconductor chips is performed at the semiconductor wafer level. CONSTITUTION:B stage curing type resin 32 is applied by printing on the back surface of a semiconductor wafer 31. The resin 32 is temporarily cured by performing a heating treatment and bonded to a base substrate 34, for example, to a silcon wafer, through water-soluble bonding agent 33. Notches 36 are cut in the resin 32 by a dicing saw for dividing into semiconductor chips 35. Then, the whole assembled unit consisting of the semiconductor wafer 31 and the base substrate 34 is dipped in water 38 in a container 37 in this state and the semiconductor chips 35 are separated from the base substrate 34, thereby enabling to obtain individual semiconductor chips 35 with the B stage cured resin.

Description

【発明の詳細な説明】 (発明の技術分野) 本発明は半導体ウェハから効率良く半導体チンプを得る
ための半導体チップの製作方法に関する。
DETAILED DESCRIPTION OF THE INVENTION (Technical Field of the Invention) The present invention relates to a semiconductor chip manufacturing method for efficiently obtaining semiconductor chips from a semiconductor wafer.

(従来技術の説明) 先ず、従来の半導体チップの完全切断方法と、ダイスポ
ンディング用Bステージ硬化タイプの樹脂の供給方法に
つき、第1図及び第2図(a)及び(b)に治って説明
する。
(Description of Prior Art) First, a conventional method for completely cutting a semiconductor chip and a method for supplying a B-stage hardening type resin for die bonding will be explained using FIGS. 1 and 2 (a) and (b). do.

この第1IΔは断面図であり、先ず、半導体ウェハを支
持板に固定するため支持板13(例えばシリコンウェハ
)を加熱し、接着剤12(例えばワックス)を溶かして
半導体ウェハを支持板13に固着させる。
This first IΔ is a cross-sectional view. First, in order to fix the semiconductor wafer to the support plate, the support plate 13 (for example, a silicon wafer) is heated, the adhesive 12 (for example, wax) is melted, and the semiconductor wafer is fixed to the support plate 13. let

次に、これをグイシングツ−を用い、切り込み深さが支
持板13に届くまで入れて完全切断を行い、その後再び
支持板13を加熱して接着剤12を溶融させて分割した
チップ11を支持板13から分離させる。次に、この半
導体チップ11に刺着した接着剤12を洗浄するために
、半導体チップIIを有機溶媒(例えばトリクレン)で
ボイリング洗浄を行う。次に、第2図(a)(平面図)
及び第2図(b)(第2図の側面図)に示すように、完
全に分割した半導体チンプ21をトレイ22の中に並べ
てスクリーン印刷手段でBステージタイプ樹脂を半導体
チップ21の裏面に供給し、100’0X30分の加熱
処理を施してダイスポンド樹脂の仮硬化を完了させ、よ
って、半導体チップ21をダイスポンディング工程へ進
めることができる。
Next, use a cutting tool to make a complete cut by making a cut until the depth reaches the support plate 13. Then, the support plate 13 is heated again to melt the adhesive 12 and the divided chips 11 are placed on the support plate. Separate from 13. Next, in order to clean the adhesive 12 stuck to the semiconductor chip 11, the semiconductor chip II is subjected to boiling cleaning with an organic solvent (for example, trichlene). Next, Figure 2 (a) (plan view)
And as shown in FIG. 2(b) (side view of FIG. 2), the completely divided semiconductor chips 21 are arranged in a tray 22, and B-stage type resin is supplied to the back side of the semiconductor chips 21 by screen printing means. Then, a heat treatment of 100'0 x 30 minutes is performed to complete the temporary curing of the die bonding resin, so that the semiconductor chip 21 can proceed to the die bonding process.

このように、従来の方法では、ウェハから半導体チップ
に完全に切断してから個別に半導体チップに樹脂を印刷
供給するため、(1)切断後のチップの取外し、(2)
洗浄、(3)樹脂の印刷の各々の際に、バラバラになっ
た半導体チップを取り扱うこととなり、これがため、ハ
ンドリング性が悪くかつ工数がかかり、製作効率が悪い
という欠点があった。
In this way, in the conventional method, the semiconductor chips are completely cut from the wafer and then resin is printed and supplied to the semiconductor chips individually.
During each of cleaning and (3) resin printing, it is necessary to handle the semiconductor chips in pieces, which has disadvantages in that handling is poor, man-hours are required, and production efficiency is poor.

また、ウェハ段階でBステージタイプ樹脂を印刷供給し
、100℃X30分の加熱処理を施してBステージ化し
た後、ワックスを介して支持板に接着し、次いで、グイ
シングツ−でゝr、導体ウェハに切り込みを行ったのち
に加熱して支持板からウェハをはずし、然る後、有機溶
媒でボイリングして接着剤の洗浄を行っているため、B
ステージが加熱溶剤に溶解されるというダメージを受け
、ダイスボンディングが不可能となる欠点があった。
In addition, at the wafer stage, a B-stage type resin is printed and supplied, heat-treated at 100°C for 30 minutes to form a B-stage, and then bonded to a support plate via wax, and then heated with a guising tool to the conductor wafer. After cutting the wafer, the wafer is heated and removed from the support plate, and then boiled with an organic solvent to clean the adhesive.
The disadvantage was that the stage was damaged by being dissolved by the heated solvent, making die bonding impossible.

(発明の目的) 本発明はこのような従来方法の欠点を除去するために成
されたもので、従って本発明の目的は効率良くかつ高精
度で半導体チップを製作できる方法を提供するにある。
(Objective of the Invention) The present invention has been made to eliminate the drawbacks of such conventional methods, and therefore, an object of the present invention is to provide a method that can manufacture semiconductor chips efficiently and with high precision.

(発明の構成) この1]的の達成を図るため、本発明の半導体チップの
製作方法によれば、半導体ウェハの裏面にBステージ硬
化タイプの樹脂を塗41シてこれを加熱硬化した後、こ
の半導体ウェハを水溶性接着剤を介してベース基板に固
着し、然るのち少なくともこの半導体ウェハ及び樹脂に
対し半導体チップに分割するための切り込みを入れ、次
に、このベース基板とこれに固着されている半導体ウェ
ハとの全体を水中に入れて半導体チップをベース基板か
ら分離さて所定の個別の半導体チップに分割するこを特
徴とする。
(Structure of the Invention) In order to achieve the objective 1), according to the semiconductor chip manufacturing method of the present invention, after coating the back surface of a semiconductor wafer with a B-stage curing type resin and curing it by heating, This semiconductor wafer is fixed to a base substrate via a water-soluble adhesive, and then at least the semiconductor wafer and the resin are cut to be divided into semiconductor chips. The method is characterized in that the entire semiconductor wafer is placed in water, and the semiconductor chips are separated from the base substrate and divided into predetermined individual semiconductor chips.

(実施例の説明) 以下、第3図(a)〜(e)基づいて本発明の実施例に
つき説明する。第3図(a)〜(e)は本発明の詳細な
説明するための製作工程図であって、夫々各製作段階で
の状態を断面図で示しであるが、本発明が理解できる程
度に概略的に示しであるにすぎない。
(Description of Examples) Hereinafter, examples of the present invention will be described based on FIGS. 3(a) to (e). FIGS. 3(a) to 3(e) are manufacturing process diagrams for explaining the present invention in detail, and each shows the state at each manufacturing stage as a cross-sectional view, but it is sufficient to understand the present invention. This is only a schematic representation.

先ず、第1図(a)に示すように、゛1616中ェハ3
1の裏面にBステージ硬化タイプの樹脂32を印刷’4
113 した後これを、例えば、約100℃の温度で約
30分間加熱処理して仮硬化される。次に、第2図(b
)に示すように、この樹脂付き半導体ウェハ31を水溶
性接着剤33を介して樹脂32側をベース基板34、例
えば、シリコンウェハに接着し、例工ば。
First, as shown in FIG. 1(a),
B-stage hardening type resin 32 is printed on the back side of 1'4
113, this is heat-treated for about 30 minutes at a temperature of, for example, about 100° C. for temporary hardening. Next, Figure 2 (b
), this resin-coated semiconductor wafer 31 is bonded with the resin 32 side to a base substrate 34, for example, a silicon wafer, via a water-soluble adhesive 33.

約80°Cの温度で約30分間加熱処理して固定する。It is fixed by heat treatment at a temperature of about 80°C for about 30 minutes.

次に、第3図(c)に示すように、グイシングツ−で半
導体ウェハ31. Bステージ硬化樹脂32及び水溶性
接着剤33に崖導体チップ35に分割するための切り込
み36を入れ、これらを完全に切断する。この段階では
各半導体チップ35は末だベース基板34に固定されて
いる。
Next, as shown in FIG. 3(c), the semiconductor wafer 31. Cuts 36 are made in the B-stage cured resin 32 and water-soluble adhesive 33 to divide them into cliff conductor chips 35, and these are completely cut. At this stage, each semiconductor chip 35 is still fixed to the base substrate 34.

次に、この状態の半導体ウェハ31及びベース基板34
の組立体全体を、第3図(d)に示す、ように。
Next, the semiconductor wafer 31 and base substrate 34 in this state are
The entire assembly is shown in FIG. 3(d).

容器37中の水38、例えば、純水中に侵漬して、例え
ば、約12〜24時間に亘って放置する。
It is immersed in water 38, for example pure water, in a container 37 and left for about 12 to 24 hours, for example.

このようにすれば、第3図(e)に示すように、Bステ
ージ硬化樹脂イ1きの個別の半導体チップ35が得られ
る。
In this way, as shown in FIG. 3(e), individual semiconductor chips 35 made of B-stage cured resin can be obtained.

(発明の効果) 上述したところから明らかなように、本発明による半導
体チップの製作方法によれば、半導体ウェハの表面にB
ステージ硬化タイプ樹脂を塗布してこれを加熱硬化させ
、次いで、これを水溶性接着剤を介してベース基板に固
定し、然る後、半導体チップに分割するため少なくとも
半導体ウェハ及び硬化樹脂に切り込みを入れてこれを水
中に入れ、よって、個別の半導体チップに分割するよう
に成したのであるから、チンプに対するBステージ・硬
化タイプ樹脂の供給をウェハレベルで行え、これがため
、従来のチップ単位の作業に比べてハンドリング性が極
めて良くなると共に各作業工数の大幅な削減が計れ、従
って、半導体チップの製作効率が著しく向上するという
利点がある。
(Effects of the Invention) As is clear from the above, according to the semiconductor chip manufacturing method of the present invention, B is added to the surface of the semiconductor wafer.
A stage curing type resin is applied and cured by heating, and then this is fixed to a base substrate via a water-soluble adhesive. After that, at least the semiconductor wafer and the cured resin are cut in order to be divided into semiconductor chips. By placing the chips in water and dividing them into individual semiconductor chips, the supply of B-stage hardening type resin to the chimps can be done at the wafer level, which eliminates the need for conventional chip-by-chip operations. This method has the advantage that the handling properties are extremely improved compared to the conventional method, and the number of man-hours required for each operation can be significantly reduced, resulting in a marked improvement in semiconductor chip manufacturing efficiency.

また、チップとペース基板との固着を水溶性接着剤を用
いて行っているので、従来のような有機溶媒を用いたボ
イリングによらずして、水中でチップの分離が行え、こ
れがため、Bステージ硬化樹脂が溶解したりしてチップ
がダメージを受る恐れが無いという利点がある。
In addition, since the chip and the paste substrate are fixed using a water-soluble adhesive, the chip can be separated underwater without boiling using an organic solvent as in the past. This has the advantage that there is no risk of damage to the chip due to melting of the stage curing resin.

また、本発明によれば、高精度なグイシングが可能とな
り、また、半導体チップ形成後のダイスポンディングの
作業工程に対するチップ取り扱い作業も簡単かつ容易と
なる。
Further, according to the present invention, highly accurate guising becomes possible, and the chip handling operation for the die-sponging process after semiconductor chip formation becomes simple and easy.

本発明はこのような利点を有するので、高精度なマルチ
ンプモジュールの組立に広く利用することが出来る。
Since the present invention has such advantages, it can be widely used in assembling high-precision multi-chip modules.

【図面の簡単な説明】[Brief explanation of drawings]

第1図及び第2図(a)及び(b)は従来の半導体チッ
プの製作方法を説明するための線図、第3図(a)〜(
e)は本発明の半導体チップの製作方法の一実施例を説
明するための製作工程図である。 31・・・半導体ウェハ 32・・・Bステージ硬化タイプ樹脂 33・・・水溶性接着剤 34・・・ベース基板35・
・・半導体チップ 36・・・切り込み37・・・容器
 38・・・水。 特許出願人 沖電気工業株式会社 第1図 L! 第2図 第3図 (e) 5
Figures 1 and 2 (a) and (b) are diagrams for explaining the conventional semiconductor chip manufacturing method, and Figures 3 (a) to (
e) is a manufacturing process diagram for explaining one embodiment of the method for manufacturing a semiconductor chip of the present invention. 31... Semiconductor wafer 32... B stage curing type resin 33... Water-soluble adhesive 34... Base substrate 35.
...Semiconductor chip 36...Notch 37...Container 38...Water. Patent applicant Oki Electric Industry Co., Ltd. Figure 1 L! Figure 2 Figure 3 (e) 5

Claims (1)

【特許請求の範囲】[Claims] 半導体ウェハの裏面にBステージ硬化タイプの樹脂を塗
布し、該樹脂を加熱硬化した後前記半導体ウェハを水溶
性接着剤を介してベース基板に固着し、然るのち少なく
とも前記半導体ウェハ及び前記樹脂を半導体チップに分
割するための切り込みを入れ、次に、前記ベース基板と
これに固着されている半導体ウェハとの全体を水中に入
れて前記半導体チップを前記ベース基板から分離させる
こを特徴とする半導体チップの製作方法。
A B-stage curing type resin is applied to the back surface of a semiconductor wafer, and after the resin is heated and cured, the semiconductor wafer is fixed to a base substrate via a water-soluble adhesive, and then at least the semiconductor wafer and the resin are bonded. A semiconductor characterized in that a cut is made to divide the semiconductor chips, and then the entire base substrate and the semiconductor wafer fixed thereto are placed in water to separate the semiconductor chips from the base substrate. How to make chips.
JP58144666A 1983-08-06 1983-08-06 Manufacture of semiconductor chip Granted JPS6035531A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58144666A JPS6035531A (en) 1983-08-06 1983-08-06 Manufacture of semiconductor chip

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58144666A JPS6035531A (en) 1983-08-06 1983-08-06 Manufacture of semiconductor chip

Publications (2)

Publication Number Publication Date
JPS6035531A true JPS6035531A (en) 1985-02-23
JPH0342506B2 JPH0342506B2 (en) 1991-06-27

Family

ID=15367401

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58144666A Granted JPS6035531A (en) 1983-08-06 1983-08-06 Manufacture of semiconductor chip

Country Status (1)

Country Link
JP (1) JPS6035531A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5358590A (en) * 1992-04-08 1994-10-25 Sony Corporation Method of manufacturing individual element arrays
JPH0828221A (en) * 1994-07-14 1996-01-30 Korea Inst Of Mach & Metals 2-Scavenging control mechanism for improving scavenging of stroke engine
EP0715341A1 (en) 1994-11-29 1996-06-05 LINTEC Corporation Method of preventing a transfer of adhesive substance to a ring frame in a dicing process, pressure-sensitive adhesive sheet and wafer support comprising said pressure-sensitive adhesive sheet
JP2003532291A (en) * 2000-04-26 2003-10-28 テレフオンアクチーボラゲツト エル エム エリクソン(パブル) Method of forming conductive paint in semiconductor device

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4917965A (en) * 1972-06-07 1974-02-16

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4917965A (en) * 1972-06-07 1974-02-16

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5358590A (en) * 1992-04-08 1994-10-25 Sony Corporation Method of manufacturing individual element arrays
JPH0828221A (en) * 1994-07-14 1996-01-30 Korea Inst Of Mach & Metals 2-Scavenging control mechanism for improving scavenging of stroke engine
EP0715341A1 (en) 1994-11-29 1996-06-05 LINTEC Corporation Method of preventing a transfer of adhesive substance to a ring frame in a dicing process, pressure-sensitive adhesive sheet and wafer support comprising said pressure-sensitive adhesive sheet
JP2003532291A (en) * 2000-04-26 2003-10-28 テレフオンアクチーボラゲツト エル エム エリクソン(パブル) Method of forming conductive paint in semiconductor device
JP2012212886A (en) * 2000-04-26 2012-11-01 Infineon Technologies Ag Method of forming conductive coating on semiconductor device

Also Published As

Publication number Publication date
JPH0342506B2 (en) 1991-06-27

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