JPS6035535A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS6035535A JPS6035535A JP14369483A JP14369483A JPS6035535A JP S6035535 A JPS6035535 A JP S6035535A JP 14369483 A JP14369483 A JP 14369483A JP 14369483 A JP14369483 A JP 14369483A JP S6035535 A JPS6035535 A JP S6035535A
- Authority
- JP
- Japan
- Prior art keywords
- film
- layer
- insulating film
- wiring
- forming
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 11
- 238000004519 manufacturing process Methods 0.000 title claims description 6
- 239000011521 glass Substances 0.000 claims abstract description 20
- 239000000758 substrate Substances 0.000 claims abstract description 7
- 238000001312 dry etching Methods 0.000 claims abstract description 3
- 238000009413 insulation Methods 0.000 claims description 5
- 238000004528 spin coating Methods 0.000 claims description 5
- 230000015572 biosynthetic process Effects 0.000 claims description 4
- 238000013007 heat curing Methods 0.000 claims description 2
- 235000010627 Phaseolus vulgaris Nutrition 0.000 claims 1
- 244000046052 Phaseolus vulgaris Species 0.000 claims 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 32
- 229910052782 aluminium Inorganic materials 0.000 abstract description 26
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 abstract description 26
- 239000000377 silicon dioxide Substances 0.000 abstract description 16
- 238000000034 method Methods 0.000 abstract description 13
- 238000005229 chemical vapour deposition Methods 0.000 abstract description 3
- 238000005530 etching Methods 0.000 abstract description 2
- 238000010438 heat treatment Methods 0.000 description 7
- 229920002120 photoresistant polymer Polymers 0.000 description 5
- 238000007796 conventional method Methods 0.000 description 3
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 239000004020 conductor Substances 0.000 description 2
- 239000007789 gas Substances 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 229910052698 phosphorus Inorganic materials 0.000 description 2
- 239000011574 phosphorus Substances 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 210000001364 upper extremity Anatomy 0.000 description 2
- 235000017166 Bambusa arundinacea Nutrition 0.000 description 1
- 235000017491 Bambusa tulda Nutrition 0.000 description 1
- 241001330002 Bambuseae Species 0.000 description 1
- 101100008044 Caenorhabditis elegans cut-1 gene Proteins 0.000 description 1
- 235000015334 Phyllostachys viridis Nutrition 0.000 description 1
- 102100037547 Semenogelin-2 Human genes 0.000 description 1
- 101710089335 Semenogelin-2 Proteins 0.000 description 1
- 239000011425 bamboo Substances 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 238000001723 curing Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- NBVXSUQYWXRMNV-UHFFFAOYSA-N fluoromethane Chemical compound FC NBVXSUQYWXRMNV-UHFFFAOYSA-N 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 238000010030 laminating Methods 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 238000005245 sintering Methods 0.000 description 1
Landscapes
- Local Oxidation Of Silicon (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【発明の詳細な説明】
（技術分野）
この発ゆＪ１’Ｊ牛導体装置の！Ｉ＋？！途方法、特に
スピン塗布と加熱硬化によってスピンコードガラスＩｌ
ｌ形成することによシ平担な表面を得るようにした多層
配線構造の半導体装１首の製造方法に関するものである
。[Detailed Description of the Invention] (Technical Field) This J1'J cow conductor device! I+? ! In particular, spin-coated glass Il can be prepared by spin coating and heat curing.
The present invention relates to a method for manufacturing a single semiconductor device having a multilayer wiring structure in which a flat surface is obtained by forming a flat surface.
（従来技術）
半導体装詐の高集積化に伴い多層配線構造にすることが
必要となってくる。この多層配線は、絶縁膜と配＃ｉ！
層とを積層して形成される。(Prior Art) As semiconductor devices become more highly integrated, it becomes necessary to use a multilayer wiring structure. This multilayer wiring consists of an insulating film and an interconnect #i!
It is formed by laminating layers.
従来の多層配線の形成方法を第１図によυ説明する。第
１図において、１は半導体基板であり、まず、この基板
１上にＰＳＧＩＩＡ（ＩＪン奮含んだ５ｉ（ｈ膜）２を
形成する。次に、こりＰＳＧＩ換２上に厚さ４０００〜
１００ＯＯＡの第１層アルミニウム配＃３’を形成する
。しかる後、そのアルミニウム配線３上を含む前記１）
Ｓ Ｇ膜２上に、貞１ｊ記アルミニウム配＆＋３とｔ
まは回じ膜厚のＰＳＧ股の絶縁膜４を形成する。そのゼ
、・、絶＃−１」弥４上に１約１ＯＯＯＯＸ厚の第２層
アルミニウム配線形成用のアルミニウム層５全形成し、
アルミニウム層５上にはフォトレジスト６を塗布−Ｊ−
る。そして、このフォトレジスト６を霧光・現像してノ
ターン化し、このパターン化されたフ第１・レジスト全
マスクとしてアルミニウムｒｔｉ５＊エツチングするこ
とによシ第２層アルミニウム配線を形成丁ゐ。A conventional method for forming multilayer wiring will be explained with reference to FIG. In FIG. 1, reference numeral 1 denotes a semiconductor substrate. First, a PSGIIA (5i (h film) containing IJ) 2 is formed on this substrate 1. Next, a PSGIIA (5i (h) film containing IJ) 2 is formed to a thickness of 4,000 to 4000 nm.
A first layer aluminum layer #3' of 100OOA is formed. After that, the above 1) including the top of the aluminum wiring 3
On S G film 2, aluminum plate &+3 and t
Then, an insulating film 4 on the PSG crotch is formed to have a thickness similar to that of the PSG film. The aluminum layer 5 for forming the second layer aluminum wiring with a thickness of about 1 OOOOX is completely formed on the 4th layer 4,
Coating photoresist 6 on aluminum layer 5 -J-
Ru. Then, this photoresist 6 is developed with fog light and developed to form a no-turn pattern, and the patterned first resist is then etched using aluminum RTI5* as a mask to form a second layer of aluminum wiring.
このような形成法では、第１層アルミニウム配線３によ
る段差のために、その上に形成される絶縁膜４に急峻な
段差が生じる。特にひどいときは、段差部の下端に凹状
のへこみ、が形成さ！しる。したがって、絶縁膜４土に
アルミニウム層５を形成したにＪ、’、合、絶縁膜４の
路肩部分７て段切れｔ起すことがある。また、アルミニ
ウム層５をバターニングづるためにフォトレジスト層６
全露光・現像したＭ÷合に、アルミニウム層５の段差部
の側少部に未露光部分８が発生してレジストが残り、ア
ルミニウム層５のエツチングのときにエツチング残りが
生じるので、短絡の原因となった。In such a formation method, the step caused by the first layer aluminum wiring 3 causes a steep step in the insulating film 4 formed thereon. In particularly severe cases, a concave dent is formed at the bottom edge of the step! Sign. Therefore, if the aluminum layer 5 is formed on the insulating film 4, a break may occur at the shoulder portion 7 of the insulating film 4. Additionally, a photoresist layer 6 is applied to pattern the aluminum layer 5.
When M÷ is fully exposed and developed, an unexposed portion 8 is generated on the side of the stepped portion of the aluminum layer 5 and resist remains, and when the aluminum layer 5 is etched, an etching residue is generated, which causes a short circuit. It became.
このような欠点を・防ぐ方法として龜、できるだり第１
／Ｆ７配線の上の絶縁タケ３１′−担化して、段差を
少ムくすることが必要である。The first method to prevent such drawbacks is to
It is necessary to make the insulating bamboo 31' on top of the /F7 wiring to reduce the height difference.
平担化する方法の１つとして、スピンコードガラス膜の
形成法がある。第２図は、その方法を適用して多層配線
を形成した図である。この場合は、第１層アルミニウム
配線３全形成した後、スピン塗布ト加熱硬化にょシスビ
ンコートカシスＩＮ、７ことえはリンを含むシリカフィ
ルム９を形成し、その後、絶縁膜４を化学気相成長法（
ＣＶ Ｄ法） ｐｔ二より形成し、以後、第１図と同ト
）＜にフる。One method for flattening is a method of forming a spin code glass film. FIG. 2 is a diagram showing a multilayer wiring formed by applying this method. In this case, after the first layer aluminum wiring 3 is completely formed, a silica film 9 containing phosphorus is formed by spin coating and heating hardening, and then a silica film 9 containing phosphorus is formed, and then the insulating film 4 is coated by chemical vapor deposition. Growth method (
(CVD method) pt2, and hereinafter the same as in Fig. 1).
このような方法によれば、スピン塗布によるシリカフィ
ルム９の表面形状が平Ｊｉｌになるので、ＣＶＤ絶縁膜
４も平■」となυ、その結果として上述の欠点全除去で
きる。According to this method, since the surface shape of the silica film 9 formed by spin coating becomes flat, the CVD insulating film 4 also becomes flat, and as a result, all of the above-mentioned defects can be removed.
しかるに、上記の従来の方法では、シリカフィルム９形
成後の熱処μｍ（時、たとえは第２層配線形成■、ｉの
シンター１積に発生する第１層配前脚ルミニウムのヒロ
ックのためしこ、第３図に示すようＶＣｌそのヒロック
１０を核とじてシリカフィルム０にクラック１１が入り
、ひどい時は、それか原因して、ＣＶｌ）絶縁膜４に−
までクラックが入るという欠点があった。However, in the above-mentioned conventional method, the heat treatment after forming the silica film 9 (for example, the hillock of the first layer lead aluminum that occurs in the sintering product of the second layer wiring formation) , as shown in FIG. 3, a crack 11 occurs in the silica film 0 with the VCl hillock 10 as the core, and in severe cases, due to this, the CVl) insulating film 4 -
The problem was that cracks could form.
（発明の目的）
この発明は上記の点に鑑みないれたもので、スピンコー
ドガラス脱形成後の熱処理時ＩＣ発生する配線層表面の
ヒロックによってガラス膜にクシツクが生じること全防
止した半導体装１白−の製逍カ陳を提供することを目的
とする。(Object of the Invention) The present invention has been made in view of the above points, and provides a semiconductor device 1 which completely prevents the formation of cracks in the glass film due to hillocks on the surface of the wiring layer that occur during heat treatment after spin code glass is removed. The purpose is to provide the production power of white.
（実施例）
以下この発［ｌ！＋］の一実施例を第４１を瓢照して説
明す不。(Example) Below is this statement [l! +] An example of this will be explained with reference to the 41st example.
第４図（ａ）において、２１はシリコン半導体基板であ
る。まず、この半導体基＆２１上に第１の絶縁１次とし
てｌ） Ｓ Ｇ膜２２を形成する。次に、この１） Ｓ
Ｇ Ｍ２２上ｖｒ３（足部分に厚さ４ｏｏｏ 〜１ｏ
ｏｏｏＸの第１層アルミニウム配線２：う（第１の配Ｎ
Ｍｆｖｉ）を形成する。しかる後、このアルミニウム配
線２３士を含む前記ＰＳＧ膜２膜上２上スピン塗イ（１
と加熱硬化によりシリカフィルム２４（スヒンコ−トカ
ラス膜）を形成する、（第４図（ａ））
このシリカフィルム２４の形成には、−例として、アル
コール浴液に５ｔ（ＯＨ）ａ葡５ｉ（ｈ換カで約４．８
％含むもの一金用いる。この溶液は、溶媒が蒸発乾燥す
ると、Ｓｉ （ＯＲ）４ →５ｉＯｚ ｆ ２Ｈ２０（
７）反応式により二酸化珪素層を形成する。この反応は
常温でおる程度反応するが、不充分でめる。こり反応を
完全にするためには加熱することが必要である。下層に
アルミニウム前脚がある場合、加熱温度は約４５０℃以
下が適当である。加熱は、浴液のスピン塗布後に約２５
０ ’Ｇで行われ、さらに後述する絶縁膜（ＣＶＤ ）
）ＳＧＩＩ巳−りの生成時にも約４５０℃によって行わ
れる。In FIG. 4(a), 21 is a silicon semiconductor substrate. First, the SG film 22 is formed as a first insulating layer on the semiconductor substrate &21. Next, this 1) S
GM M22 upper VR3 (thickness 4ooo ~ 1o on the foot part)
oooX first layer aluminum wiring 2: U (first wiring N
Mfvi) is formed. After that, spin coating (1
A silica film 24 (shine coated glass film) is formed by heating and curing (FIG. 4(a)). To form this silica film 24, for example, 5t (OH) Approximately 4.8 in h exchange power
Use the entire amount including %. This solution becomes Si(OR)4 →5iOz f 2H20(
7) Form a silicon dioxide layer using a reaction formula. This reaction occurs to some extent at room temperature, but is insufficient. Heating is necessary to complete the reaction. If there is an aluminum front leg in the lower layer, a suitable heating temperature is about 450°C or less. Heating is approximately 25 minutes after spin application of the bath solution.
Insulating film (CVD) performed at 0'G and described later
) The temperature is also about 450° C. during the production of SGII resin.
このようにしてシリカフィルム２４を形成したならは、
次に、フッ化炭素系のガスたとえはＣ，Ｆ。If the silica film 24 is formed in this way,
Next, examples of fluorocarbon gases are C and F.
などのガスによシ、第１層アルミニウム配、ｌｌ！１１
２３の上部表面が現われるまでシリカフィルム２４を全
面ドライエツチングする。これによシ、第１層アルミニ
ウム配線２３上にはシリカフィルム２４がなくなる。（
８１４４図（ｂ））
しかる後、第１層アルミニウム前約２３上金含むシリカ
フィルム２４上にＣＶＤ ＰＳＧ ＃のｉｈ膜２５（第
２の絶縁膜）を、第１層アルミニウム配線２３とはは同
じ膜厚に形成し、この絶縁Ｉｔ！４２５上には第２層ア
ルミニウム配線２６を形成する。For gases such as, the first layer aluminum layer, ll! 11
The entire surface of the silica film 24 is dry etched until the upper surface of 23 is exposed. This eliminates the silica film 24 on the first layer aluminum wiring 23. (
(Fig. 8144(b)) After that, a CVD PSG # IH film 25 (second insulating film) is placed on the gold-containing silica film 24 about 23 times above the first layer aluminum, which is the same as the first layer aluminum wiring 23. This insulation It! A second layer aluminum wiring 26 is formed on the layer 425.
（発明の効果）
以上の一実施例から明らかなように、こり九明の方法で
は、スピンコードガラス膜を形成した後に、このスピン
コードガラス膜全全面ドライエツチングして、スピンコ
ードガラスミｔ第１の配線層上からは取シ除く。すなわ
ち、スピンコードガラス膜のクラックが生じる部分を除
去するのである。したがって、第１の配線層に発生する
ヒロックによって以前のようにスピンコードガラス膜に
クラックが生じることはなくなり、勿論、その上の第２
の絶縁膜にクラックが生じることもない。(Effects of the Invention) As is clear from the above embodiment, in Korikumi's method, after forming a spin code glass film, dry etching is performed on the entire surface of the spin code glass film. Remove it from above wiring layer 1. That is, the portions of the spin cord glass film where cracks occur are removed. Therefore, hillocks generated in the first wiring layer no longer cause cracks in the spin code glass film as before, and of course
No cracks occur in the insulating film.
また、スピンコードガラス膜全全面ドライエツチングす
るため、表面形状ｔよほとんど変らず平担である。した
がって、その上に形成する第２の絶縁膜や第２の配線層
用金属層は一様な平担な表面を形成することが可能とな
り、急峻な段差に゛よって生じる第２の配線層の断か１
（や短絡を防ぐことができる。In addition, since the entire surface of the spin code glass film is dry etched, the surface shape is almost unchanged from t and is flat. Therefore, the second insulating film and the metal layer for the second wiring layer formed thereon can form a uniform and flat surface, and the second wiring layer formed by the steep step difference can be Cut 1
(This can also prevent short circuits.
さらに、第２の配＃Ｊ層用金柘）〜の表面が平担になれ
は、その表面上に形成するパターン化のためのフォトレ
ジスト層としても凹凸のない均一な膜厚のものが得られ
るので、高精度なフォトレジストマスク／ぐターンを得
ることもできるようになる。Furthermore, if the surface of the second metal layer J layer is flat, the photoresist layer for patterning formed on the surface can have a uniform thickness without any unevenness. This makes it possible to obtain highly accurate photoresist masks/patterns.
第１図は従来の多層配線の形成方法を説明１−るための
断面図、第２図は従来の他の多ノ會前脚の形成方法全貌
間するための断面図、第３図は第２図の他の方法におい
てシリカフィルムにクラックが生じる様子を示す平面図
、第４図はこの発明の半導体装１６の製造方法の一実施
例を説明するための断面囚である。
２１・・・シリコン生導体基板、２２・・・ＰＳＧ膜、
２３・・・第１層アルミニウム配線、２４・・・シリカ
フィルム、２５・・・絶縁膜、２６・・・第２層アルミ
ニウム配線。
ｌ持Ｗ１出願人 沖■、気工業株式会社第１図
第；３図
第４図
３
＋１１１１＋Fig. 1 is a cross-sectional view for explaining the conventional method for forming multi-layer wiring, Fig. 2 is a cross-sectional view for explaining the overall method for forming another conventional multilayer front leg, and Fig. FIG. 4 is a plan view showing how cracks occur in the silica film in the other method shown in the figure, and is a cross-sectional view for explaining one embodiment of the method for manufacturing the semiconductor device 16 of the present invention. 21... Silicon raw conductor substrate, 22... PSG film,
23... First layer aluminum wiring, 24... Silica film, 25... Insulating film, 26... Second layer aluminum wiring. Holder W1 Applicant Oki ■, Ki Kogyo Co., Ltd. Figure 1; Figure 3 Figure 4 Figure 3 +1111+
Claims (1)
１の絶縁股上に第１の違己４策層を形成する工程と、こ
の第１の配ｆｉＩＪｒ？ｊ上を含む前記第１０絶縁膜上
Ｋ、スピン塗布と加熱硬化にょシスビンコートガラス膜
を形成する工程と、ぞのスピンコードガラスＩＭを、前
記第１の配ｌ１ｌｉ！層の上部表面が現われるまでドラ
イエツチングするコニイ）！と、そのｕコ、ｎ１ｆＦａ
ｔ：ｇＰ、ｘの配線層上を含む前Ｈ【１スピンコードガ
ラス膜上に第２の絶縁膜を形成する工程とを具備するこ
とを／Ｉ？徴とする半導体製餡の製造方法。[Claims] First insulation B on the semiconductor substrate! After the complete formation of A, a step of forming a first insulation layer on this first insulation crotch, and a step of forming this first insulation layer. A step of forming a spin coating and heat-curing glass coated glass film on the tenth insulating film including the above-mentioned first insulating film K, and a step of forming a spin cord glass IM on the first insulating film K, including the above-mentioned first insulating film K, and a step of forming a spin coat glass film on the tenth insulating film K including the above-mentioned first insulating film. Dry etching until the top surface of the layer appears)! And that u co, n1fFa
/I? A manufacturing method for semiconductor-made bean paste.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14369483A JPS6035535A (en) | 1983-08-08 | 1983-08-08 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14369483A JPS6035535A (en) | 1983-08-08 | 1983-08-08 | Manufacture of semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6035535A true JPS6035535A (en) | 1985-02-23 |
| JPH0449258B2 JPH0449258B2 (en) | 1992-08-11 |
Family
ID=15344786
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP14369483A Granted JPS6035535A (en) | 1983-08-08 | 1983-08-08 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6035535A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62295437A (en) * | 1986-06-14 | 1987-12-22 | Yamaha Corp | Forming method for multilayer interconnection |
| JPS6365646A (en) * | 1986-09-05 | 1988-03-24 | Nec Corp | Semiconductor device |
| EP0636937A1 (en) | 1993-07-28 | 1995-02-01 | Chugai Photo Chemical Co. Ltd. | Compositions of color developing agent and color developer composition for processing silver halide color photographic material and method of using the same |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS53104186A (en) * | 1977-02-23 | 1978-09-11 | Hitachi Ltd | Multilayer wiring body |
-
1983
- 1983-08-08 JP JP14369483A patent/JPS6035535A/en active Granted
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS53104186A (en) * | 1977-02-23 | 1978-09-11 | Hitachi Ltd | Multilayer wiring body |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62295437A (en) * | 1986-06-14 | 1987-12-22 | Yamaha Corp | Forming method for multilayer interconnection |
| JPS6365646A (en) * | 1986-09-05 | 1988-03-24 | Nec Corp | Semiconductor device |
| EP0636937A1 (en) | 1993-07-28 | 1995-02-01 | Chugai Photo Chemical Co. Ltd. | Compositions of color developing agent and color developer composition for processing silver halide color photographic material and method of using the same |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0449258B2 (en) | 1992-08-11 |
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