JPS6035544A - Semiconductor device - Google Patents

Abstract

PURPOSE:To prevent an operation error even if a rate of change with time of a circuit current is large by a method wherein internal leads are bifurcated into two and one of them is connected to one group of the bonding pads which are divided into two groups by a metal thin wire and another pads group is connected to another group of the internal leads. CONSTITUTION:At least either of a high potential wiring and a low potential wiring of the wirings for supplying the electric power to a circuit chip 1 is divided into two groups and each group is provided with a bonding pad. Also, the internal leads of the internal leads 4 of a package 2 which said bonding pads divied into two groups should be connected with are bifurcated into two groups 6 and 7. Then, G' which is one group of the bonding pads is connected with one group of the internal leads 6 by a metal thin wire and another group G'' of the bonding pads is connected with another group of the internal leads 7 by a metal thin wire.

Description

[Detailed description of the invention] The present invention relates to a semiconductor device.

A dual in-line pan cage (hereinafter referred to as DIP) is the most commonly used groove arrangement for semiconductor devices.

Figure 1 shows the conventional 18V/glass seal 1 with the lid removed.
) is a plan view of an IP type semiconductor device. In FIG. 1, 1 is a circuit tip, 2 is a package, 3 is an external lead terminal, 4 is an internal lead, and 5 is a thin metal wire.

FIG. 3 is an equivalent circuit diagram of the semiconductor device shown in FIG.

In FIG. 3, the part surrounded by the dotted line A represents the circuit part, the part surrounded by the dashed-dotted line B represents the circuit chip lft, the part surrounded by the dashed-dotted dot C represents the package 2, and the part surrounded by the dashed-dotted line B represents the package 2.
~Lts is the thin metal wire 5 and the internal lead 40 in FIG.
represents the self-inductance of the part, represents the bonding pad of the low potential side wiring of the G/U power supply, V' represents the bonding pad of the high potential side wiring of the power supply, and ridge represents the output bonding pad. 15' represents the input bonding pad, %G represents the terminal on the low potential side of the power supply, ■ indicates all terminals on the high potential side of the power supply, O
represents the output terminal, and 1x-115 represents the input terminal. Although there are resistance components and capacitance components in the internal leads 4 and the thin metal wires 5, as will be described later, these effects are slight, so they are ignored in this equivalent circuit.

It is well known that when the current flowing through a conductor changes over time, a back electromotive force is generated due to the self-inductance component of the conductor, which is determined by the product of the current rate of change over time and the self-inductance. There is. Now, if the magnitude of self-inductance f L is 7W and the current is i9 and 6t, then the back electromotive force φ will be i φ=−L□ i . The self-inductance of the bonding wire and the gold lead is about 20 nanoHenries at most in an 18-pin DIP. Now di/dt t-1 per nanosecond
Assuming 0 milliampere, the magnitude of φ is φ=-20X1
0 (He/Lee) XIOXl 0-3C Ampere] τ10
[seconds] = -0.2C volts]. On the other hand, the resistance component of the bonding wire and the four leads for strain is about 10 mΩ at most; h') Even if the ft current is IA, the voltage change due to the resistance is 0.01 V, which is not a problem at all. In addition, the electrostatic charge between the gold) tA thin wires and between the internal leads is about 1 pF, and 100 Mllz
Also, the reactance is 1.6Ω. On the other hand, since the impedance of the external circuit connected to the input terminal is 100Ω or less, the influence of electrostatic d-scape can be ignored.

Next, the adverse effects of the back electromotive force due to self-inductance will be explained. In Figure 3, the input terminal check l~its
A case in which the circuit operates and the power supply current changes in response to a change in the signal applied to the circuit will be described with reference to FIG.

In Fig. 5, 11 is the signal waveform applied to the input terminal, and 12 is the signal waveform applied to the input terminal.
indicates the low potential wiring current of the power supply, and 13 indicates the potential of the potential side bonding pad G' with the power supply. After the input signal changes from high level to low level or from low level to high level at time to, the internal circuit operates, and from time t1 to t2
During this period, the power supply low potential mA IE * flowing through LL7 temporarily increases. A back electromotive voltage is generated across the current at the peak 1 and across the resistor L17, and the potential at the bonding pad G' on the low 1 side of the circuit chip fluctuates as shown at 13 in FIG.

Now, the logic levels "l" and "0" of the input signal are general TTL levels, and 1" is zO volt "()" is 0.
Set to 8 volts. It is assumed that the pinch circuit always feels "0" if the input is 0.8 volts or less, and always feels 11' if the input is 2.0 volts or more. The thing to note here is usually 1.
The level at which the circuit senses llO'' is higher than 0.8 volts, and the level at which the circuit senses 'l''' is lower than 2.0 volts. Now, [the highest voltage J kVxr that the circuit feels as 0''.

If we express the "lowest voltage at which the circuit feels 1" as VIH, then the following relationship holds: 0.8 volts2VtL<VIH≦zo volts. Putting this in reverse, even if the input does not exceed 2 volts, as long as it is above VIH, the circuit will
11", and even if it does not go below 0.8 volts, if it is below VIL, it feels 0".

Now, between times t1 and 12, the inductor value L17t
l-The flowing current changes as shown in 12 in Figure 5, and as a result, the bonding voltage potential on the low potential side of the power supply of the circuit chip increases by ΔV1 volt on the negative side and ΔV on the positive side as shown in 13 in Figure 5.
Suppose it fluctuates by 2 volts.

From the perspective of the circuit chip, this appears as if the input No. 15 level had moved by ΔV1 volts to the positive side and by Δv2 volts to the negative side. Therefore, when viewed from the 5-circuit chip, if the input signal is at a low level of 0.8 volts, when the ground potential changes by Δ■1 volts to the negative side, the input signal becomes o,8+Δ■1 volts. When it appears to have changed and fluctuated by ΔV2 volts on the positive side, it is 0.8-Δ■
It looks like it's now 2 volts. Similarly, among the Jinkai δ, those at crystal level 2.0 volts appear to have become 2.0+Δ■l volts and 2.0-Δ■2 volts. As mentioned above, the circuit feels "1" if the input is above VIH, and "0" if it is below VIL. When the potential of the Tenogu's power supply low potential side wiring changes, even if the input signal is 0.8 volts, if the magnitude of the potential fluctuation Δ■1 is such that it satisfies O, S + ΔV1 = 2VIH. , the circuit will sense that the input is ``1 level'' and will malfunction, and even if the input signal is 2.0 volts, the circuit will malfunction even if the input signal is 2.0 volts. Otherwise, it will feel like it has reached the 0°" level and will malfunction.

In recent years, the crystal speed of semiconductor devices has significantly increased, and as a result, the rate of change in circuit current over time has become larger and larger, due to the self-inductance of the thin metal wires and internal leads as described above. Circuit malfunctions are becoming a very serious problem.

One possible solution to this problem is to bond the wiring with a large current change rate to a short lead.
[ifl] Usually, the semiconductor device 1lfQ terminal arrangement is standardized, and such a change is not desirable. Therefore, such fL changes are not performed, and conventional semiconductor devices whose circuit portions have a large rate of change over time have the disadvantage of often causing malfunctions.

The purpose of the present invention is to eliminate the above-mentioned drawbacks, and to prevent errors even when the time rate of change of the circuit current is large. - To provide a semiconductor device that does not require production costs.

A semiconductor device according to the present invention includes a circuit chip in which a plurality of circuit elements are formed on a semiconductor, a circuit chip having a layout connecting the plurality of circuit elements or the circuit button and a bonding pad, an external lead terminal, and a package that houses and seals the circuit chip and has an internal lead connected to the circuit chip;
A semiconductor device formed *i'J including a thin metal wire connecting the internal lead and the bonding pad,
High of wiring to power the circuit chip? At least one of the B-level wiring and the low-level wiring is divided into two groups, and a bonding pad is provided for each group, and the bonding pads are provided in the two groups among the internal leads of the package. Divide the inner lead to be electrically connected into two, connect one of the bonding pads provided in the two groups with one crotch of the inner lead with a thin metal wire, and connect the two groups. The other of the bonding pads provided on the inner lead and the other crotch of the inner lead are connected by a bent thin wire.

Next, embodiments of the present invention will be described using the drawings.

FIG. 2 is a plan view of one embodiment of the present invention.

In FIG. 2, 1 is a circuit chip, 2 is a package, 3 is an external lead terminal, 4 is an internal lead, 5 is a metal phase AL L 7 is an internal lead that is divided into two parts and connected to a power source.

An equivalent circuit of the implementation shown in FIG. 2 is shown in FIG. 2134.

In Figure 4, A is WLIAr of the circuit chip, the circuit part where the change is small, N is the circuit part of the circuit chip where the current change is large, B is the circuit chip, C is the whole pan cage gummy wash,
■1' to 115' are the input bond pads on the circuit chip, and O is the output bonding pad. What is the potential 11111 Pound/Gbad, G? Bonding band on the power supply low potential side of the circuit part when changing the IE current ratio, 11 to l15 are the input terminals of the semiconductor device, O is the output terminal, G is the low potential terminal of the power supply, ■ is the high potential terminal of the 1-line source, L1 ~L18 is the inductance kt+ of the gold wire between the bonding pad and the terminal and the inner T1μ lead.

Next, the operation of the embodiment of the present invention will be described with full reference to FIGS. 4 and 6. As in the conventional example, the input signal is at time 1o.
After the transition from 0.8 volts to 2.0 volts or from 2.0 volts to 0.8 volts, between times t1 and 12,
Assume that the power supply low potential wiring current temporarily increases. In the conventional example, this current change causes a self-inductance of 70
This is because a back electromotive force is generated at both ends, causing the power supply level of the circuit to fluctuate.

The above-mentioned process causes malfunctions. However, in the present invention, as shown in the equivalent circuit in FIG.
Divide it into a part λ where the current changes are large and a part A where it is not, and also check if the power supply is low? [Among the side wiring, there is almost no wiring that is common to the two circuit parts. In other words, the fourth
The wL current flowing through the self-inductance L17'2 shown in the figure has a small rate of change over time, and the above two circuit portions A of the power supply low full level wiring.

The self-inductance L17F of the wiring common to A' is very small. Therefore, the circuit part hv76 source low potential is the sixth
As shown by line 23 in the figure, the fluctuations are significantly smaller than in the conventional example, and stable operation can be obtained without causing malfunctions, which are a problem in the conventional example.

In addition, in the above explanation, the glass-sealed 18-bin DIP=(
However, the present invention is not only applicable to glass-sealed DIPs with pin numbers other than 18, but also resin-sealed 1) IP or DI.
Needless to say, the present invention can also be applied to borrowed semiconductor devices other than P.

As described above, according to the present invention, it is possible to obtain a semiconductor device that does not malfunction and operates stably even if the rate of change of current over time is large.

[Brief explanation of the drawing]

Fig. 1 is a plan view of a conventional 18-bottle glass-sealed semiconductor device with a moat removed. Fig. 2 is a plan view of an embodiment of the present invention. # shown in the figure; J
4 is an equivalent circuit diagram of the embodiment shown in FIG. 2; FIG. 455 is a waveform diagram for explaining the operation of the semiconductor device shown in FIG. 1; FIG. 6 is an equivalent circuit diagram of the Z-body device; 2 is a waveform chart for explaining the operation of the embodiment shown in FIG. 2. FIG. 1... Circuit chip, 2... Package, 3... External lead terminal, 4... Internal lead, 5... Waste saving A411M , 6.7...
...Internal reed divided into two branches, 11...
Input signal waveform %12...Low potential wiring current waveform of power supply, 13...Voltage waveform of low potential side bonding pad of power supply, 21...Input (i waveform 22.22'...Low f [(S''l wiring current waveform of the power supply), 23...Voltage waveform of the low potential side bonding pad of the power supply. Agent: Susumu Uchihara, patent attorney Thing 1ヅ■ 2nd sentence 3゛9

Claims (1)

[Claims] A circuit chip in which a plurality of circuit elements are formed on a semiconductor, and has wiring connecting between the plurality of circuit elements or between the circuit elements and a bonding pad, an external lead terminal, an internal lead connected thereto, and a metal layer. In a semiconductor device including a package that houses and seals the circuit chip, and thin metal wires that connect the internal leads and bonding pads, one of the wirings for supplying power to the circuit chip. At least one of the high potential wiring or the low potential wiring is divided into two groups, and a bonding pad is provided for each group, and the bonding pad provided in the two groups among the internal leads of the package is The internal lead to be electrically connected is divided into two, one of the bonding pads provided in the two groups is connected to one crotch of the internal lead with a thin metal wire, and the bonding pad provided in the two groups is connected to one crotch of the internal lead. 1. A semiconductor device, wherein the other of the bonding pads and the other crotch of the internal leads are connected to each other by all-metal hoops.