JPS6035548U - integrated circuit - Google Patents
integrated circuitInfo
- Publication number
- JPS6035548U JPS6035548U JP12649283U JP12649283U JPS6035548U JP S6035548 U JPS6035548 U JP S6035548U JP 12649283 U JP12649283 U JP 12649283U JP 12649283 U JP12649283 U JP 12649283U JP S6035548 U JPS6035548 U JP S6035548U
- Authority
- JP
- Japan
- Prior art keywords
- integrated circuit
- power supply
- pin
- package
- ground pin
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
- Semiconductor Integrated Circuits (AREA)
- Elimination Of Static Electricity (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第1図は従来の集積回路をプリント基板に実装した状態
を示す説明図、第2図はこの考案に係る集積回路をプリ
ント基板に実装した状態を示す説明図、第3図aはこの
考案の要部である集積回路のパッケージ内にパイ兵スコ
ンデンサが収納された状態を示す説明図、第3図すは第
3図aの側面図である。
1.4・・・集積回路、2,10・・・バイパスコンデ
ンサ、6・・・パッケージ、7・・・チップ、8・・・
電源ピン、9・・・グランドピン、なお、各図中、同一
符号は同一または相当部分を示す。Figure 1 is an explanatory diagram showing a state in which a conventional integrated circuit is mounted on a printed circuit board, Figure 2 is an explanatory diagram showing a state in which an integrated circuit according to this invention is mounted on a printed circuit board, and Figure 3 a is an explanatory diagram showing a state in which an integrated circuit according to this invention is mounted on a printed circuit board. FIG. 3 is an explanatory diagram showing a state in which a piezoelectric capacitor is housed in a package of an integrated circuit, which is a main part, and is a side view of FIG. 3a. 1.4... Integrated circuit, 2,10... Bypass capacitor, 6... Package, 7... Chip, 8...
Power supply pin, 9...Ground pin. In each figure, the same reference numerals indicate the same or equivalent parts.
Claims (1)
備えるパッケージ内に、所望の機能を有するチップを設
けた集積回路において、前記電源ピンとグランドピンと
の間に接続され、電源ノイズの除去を行うバイパスコン
デンサを前記パッケージ内に一体として収納したことを
特徴とする集積回路。A bypass capacitor connected between the power supply pin and the ground pin to remove power supply noise in an integrated circuit including a chip having a desired function in a package including a power supply pin and a ground pin for supplying power. An integrated circuit characterized in that the integrated circuit is housed integrally within the package.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12649283U JPS6035548U (en) | 1983-08-16 | 1983-08-16 | integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12649283U JPS6035548U (en) | 1983-08-16 | 1983-08-16 | integrated circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6035548U true JPS6035548U (en) | 1985-03-11 |
Family
ID=30287607
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP12649283U Pending JPS6035548U (en) | 1983-08-16 | 1983-08-16 | integrated circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6035548U (en) |
-
1983
- 1983-08-16 JP JP12649283U patent/JPS6035548U/en active Pending
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