JPS6035564A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To contrive to speed up the action of circuit elements by a method wherein such a layout that the resistance value of diffused layer of a drain region is not reduced or not influenced by the resistance of diffused layer of the drain region is used without the increase of the number of manufacturing processes, in each drain region of an inverter circuit composed of a CMIS. CONSTITUTION:A gate electrode 14 and a field insulation film 10 are used as a mask against impurities, and an n type impurity to form the source region S and the drain region D at the main surface part of a selected well region 9 is introduced. Then, a p type impurity to form the source region S and the drain region D at the main surface part of a selected semiconductor substrate 8 is introduced. Thereafter, elongating diffusion is carried out to the n type impurity by heat treatment, thus forming an n<+> type semiconductor region 16; elongating diffusion is carried out to the p type impurity, thus forming a p<+> type semiconductor region 17. The above-mentioned semiconductor region 13 is formed into an integral body by the elongating diffusion of the impurity to form the drain region D, and then becomes a semiconductor region 16. Next, the insulation film 18 composed of e.g. phosphorus silicate glass (PSG) is formed over the entire surface.

Description

[Detailed Description of the Invention] [Technical Field] The present invention relates to a technology that is effective when applied to semiconductor integrated circuit devices, and in particular, relates to a technology that is effective when applied to semiconductor integrated circuit devices, and in particular, a technology that is effective when applied to semiconductor integrated circuit devices, and in particular, a technology that is effective when applied to semiconductor integrated circuit devices. The present invention relates to a technique that is effective when applied to a semiconductor integrated circuit device equipped with a complementary FET (hereinafter referred to as 0Ml5).

[Background technology]

As shown in FIG.
p-channel MI 5FET electrically connected to oc
The OMI SK inverter circuit constituted by Q and an n-channel MISFET Qy whose source region S is electrically connected to the ground potential V88 is generally well known (Integrated Circuit Application Handbook, Asakura Shoten, 1981 edition, P, 74).

The specific layout of this inverter circuit may be constructed as shown in FIG.

The p-channel M I S F E T Q + has a first conductive layer electrically connected to the signal input terminals φ and N, for example, a gate electrode 1 formed of polycrystalline silicon, and both sides thereof. It is constituted by a p+ type semiconductor region 3 used as a source region S and a drain region, which are selectively provided on the main surface of the semiconductor substrate 2. The n-channel MISFETQy is the p-channel MISFETQy.
A gate integrally formed with the FET Q, and a source region S and a drain region selectively provided on the main surface of the semiconductor substrate 2 in both 9111 parts or on the main surface of the p-type well region 9. It is composed of an n" type semiconductor region 4 and K used as a p-channel MISFET.
In the source region S of Q, a voltage of cc is applied to a second conductive layer provided almost orthogonally to the gate electrode 1, a first wiring 5 formed of aluminum, for example, and a connection. Hole 0. applied via. The applied voltage is applied to the signal output terminal φ through the p-channel MISFET Q, Y, from its drain region, through the connection hole C7 and the second wiring 6 formed in the same process as the first wiring 5. □, is output. n-channel MISFET
In the drain region DVc of Q, the voltage due to the output stamped to the second wiring 6 is connected to the connection hole 0. applied via. The applied voltage is applied to the n-channel MISFETQ,
from the source region S through the connection hole 04 and the first
Through a third wiring 7 formed in the same process as the wiring 5 and provided substantially parallel to the wiring 5, the voltage becomes the same level as the ground potential V8s.

Such a specific layout has the following advantages. The first advantage is that electrical connections between the main semiconductor elements of a semiconductor integrated circuit device can be made using single-layer aluminum wiring, which reduces the number of manufacturing steps in the manufacturing process and improves yield. Therefore, it is possible to provide a semiconductor integrated circuit device that is high quality and therefore inexpensive. In particular, memory functions that require mass production and low cost? The first advantage becomes remarkable by using the above-mentioned temperature range as a layout for configuring the peripheral circuits of a semiconductor integrated circuit device. The second advantage is that the power supply terminal Vc
The first wiring 5 connected to V88 and the third wiring 7 connected to the ground potential V88 are spaced apart from each other and extend approximately parallel to each other, so that the wiring density is not reduced. ,
Furthermore, it is possible to efficiently arrange a plurality of inverter circuits, thereby providing a semiconductor integrated circuit device that is advantageous in terms of temperature and layout. Particularly, in the input/output stage, an inverter circuit whose size is larger than that inside the inverter circuit is advantageous in order to reduce the occupied area when a plurality of inverter circuits are arranged.

However, as a result of experiments and busy studies by the present inventor, the following problems are not identified when attempting to improve the operating time of the inverter circuit and speed up the semiconductor circuit device using this technology. Ta. That is,
The first wiring 5 and the third wiring 7 are
I” E T Q+ −Qt, the source region S and the drain region S and the drain region
The positions of the connection holes 0, , O, with the wiring 6 are very limited.
It means that it is tight. This problem is that in an inverter circuit, the delay in operation time is due to the large resistance value in the drain region, and the column direction diffusion layer resistance value (approximately 5 (l[Ω/gate) in the drain region. ]) cannot be ignored.

[Purpose of the invention]

The object of the present invention is to provide a solution composed of 0Ml5 °C.

An object of the present invention is to provide a semiconductor integrated circuit device that can improve the operating time of circuit elements.

The above-mentioned and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Summary of the invention]

A brief overview of typical inventions disclosed in this application is as follows.

In other words, in each drain region of the inverter circuit configured with 0Ml5, the diffusion layer resistance value of the drain region is reduced or the diffusion layer resistance of the drain region is reduced without increasing the number of manufacturing steps in the normal manufacturing process. The purpose of the present invention is to improve the operation time of an inverter circuit by using a layout that does not cause the 0Ml5 to run, thereby increasing the speed of a semiconductor integrated circuit device equipped with 0Ml5.

Hereinafter, the structure of the present invention will be explained in detail along with an embodiment.

〔Example〕

In this embodiment, a case will be explained in which the present invention is applied to an inverter circuit constituted by 0Ml5.

First, the specific structure of this example will be explained.

FIG. 3 is a diagram illustrating the structure of an embodiment of the present invention.
4 is a plan view of a main part of a semiconductor integrated circuit device equipped with Ml5, and FIG. 4 is a cross-sectional view taken along the line IV-IV in FIG. 3. In FIG. 3, an insulating film to be provided between each conductive layer is not shown in order to make the drawing easier to see.

In all subsequent figures, parts having the same function are given the same reference numerals, and repeated explanations will be omitted.

In FIGS. 3 and 4, reference numeral 8 denotes an n-type semiconductor substrate made of silicon single crystal, and is used to construct a semiconductor integrated circuit device. Reference numeral 9 denotes a p-type well region provided on a selected main surface portion of the semiconductor substrate 8, and is particularly for forming 0M15. Reference numeral 10 denotes a field insulating film provided on the main surface of the semiconductor substrate 8 or the main surface of the well region 9 between the semiconductor elements, for electrically isolating them. Reference numeral 11 denotes an insulating film other than the field insulating film 10 provided on the upper surface of a predetermined semiconductor substrate 8 or the upper main surface of the well region 9.
This is for forming a gate insulating film. 12 is an n-channel MISFETQ.

The insulating film 1 above the semiconductor region 16 which becomes the drain region of
1 is a connection hole formed by removing as much as possible in the manufacturing process, and the semiconductor region 16 that becomes the drain D.
This is to reduce the resistance value of the diffusion layer. This connection hole 12 is incorporated in a normal manufacturing process as a manufacturing step for forming a direct contact, and can be provided without increasing the number of manufacturing steps.

14 is a p-channel MIS by the first conductive layer.
FETQ, and n-chi? 7nel MISI”ETQ.

A gate electrode 14 is provided extending over a predetermined insulating film 11 of each MISFETQ+ = Q*
It is for configuring. In the p-channel MISFET Q+, the gate electrode 14 is arranged in a row direction substantially parallel to the wiring 20, which will be described later, and in the n-channel MISFET Q+.
In SF'E'l'Q, they are arranged in a column direction that is substantially perpendicular to wiring 22, which will be described later. 15 is located above the drain region (to be described later) of the connection hole 12, which is possible in the manufacturing process. This is a conductive layer provided so as to obtain a contact surface as large as C, and is used to reduce the resistance value of the diffusion layer of the semiconductor region due to the drain region.

The conductor/115 is made of the same material as the gate electrode 14, and
℃ through the same manufacturing process. 1
Reference numeral 6 denotes an n+ type semiconductor region provided on both sides of the gate electrode 14 in a predetermined well region 9, and the source region S
and the drain region is l, n f y7ne A/M
This is for configuring I5FETQ2'. The semiconductor region 16, which becomes the drain region, has a conductive body 15 provided thereon and impurities diffused from the conductive body 15, so that the substantial resistance value of the diffusion layer is reduced. It has become. Reference numeral 17 denotes a p+ type semiconductor region provided on both sides of the goo 1 pole 14 of a predetermined semiconductor substrate 8, and serves as a source region S and a train region to constitute a p-channel MISFET Q. be. Reference numeral 18 denotes an insulating film between the first conductive layer and the second conductive layer, which will be described later, for electrically isolating them. 19 is a predetermined insulating film 11.
This is a connection hole provided by selectively removing 18, and is for electrically connecting, for example, a predetermined semiconductor region and wiring to be described later. Reference numerals 20, 21, and 22 are wirings provided by the second conductive layer to extend above the predetermined insulating film 18, and are used to electrically isolate semiconductor elements, etc. . These wires 20, 21, and 22 have extremely low resistance values and are the main wires of semiconductor integrated circuit devices. The first wiring 20 is connected to the cooling terminal vcc and extends in the row direction, and connects the connection hole (0,) 19 to the source region S of the p-channel MISF"ETQ".
It is electrically connected to the semiconductor region 17. Second
The wiring 21 has one end electrically connected to the semiconductor region 16.17 which becomes a drain region via a connection hole (On=07) 19, and the other end to an output signal terminal φ. oT
K is connected. Second wiring 21 and p-channel MIS
The semiconductor region 17 serving as the drain region of FETQ+ is electrically connected to the semiconductor region 17 through as many connection holes (0,) 19 as possible.
This reduces the influence of the diffusion layer resistance. The third wiring #I22 is connected to the ground potential V8B and extends in the row direction, and is electrically connected through the connection hole (08) 19.

This embodiment is particularly effective when applied to 0Ml5, which is large in human output of semiconductor integrated circuit devices.

Next, the specific manufacturing method of this example will be explained in detail.

5 to 8 are sectional views of essential parts of a semiconductor integrated circuit device equipped with 0Ml5 in each manufacturing process for explaining a specific manufacturing method according to an embodiment of the present invention.

First, a low-type semiconductor substrate 8 made of silicon single crystal is prepared. A p-type well region 9 for forming 0M15 is formed in a selected region of the main surface of the semiconductor substrate 8. After this, as shown in FIG. 5, a field insulating film 10 for electrically isolating the semiconductor elements is selectively formed on the main surface of the semiconductor substrate 8 and the main surface of the well region 9 between the semiconductor elements. do. This field insulating film lO is the well-known L 000 S (LOOal 0x
It may be formed at 0.degree.

After the process shown in FIG.
As a final step, an insulating film 11 for forming a gate insulating film is formed. This may be formed, for example, by thermal oxidation technology. After this, the upper part of the predetermined well area 9,
Specifically, the insulating film 11 above a predetermined drain region constituting the n-channel M, ISFET is selectively removed, and a connection hole 12 is formed as shown in FIG. The formation of the contact hole 12 is used as a manufacturing step for forming a direct contact of polycrystalline silicon wiring in a normal manufacturing process, and is not added as a new manufacturing step.

After the step shown in FIG. 6, a polycrystalline silicon film serving as the 1Nth lightning conductor layer is formed over the entire surface. This polycrystalline silicon film is subjected to phosphorus treatment in order to obtain conductivity. As a result, from the connection hole 12 to the selected main surface of the well region 9,
Impurities from the phosphorus treatment are introduced to form an n+ type semiconductor region 13. After that, the polycrystalline silicon film is buttered, and as shown in FIG.
A gate electrode 14 constituting the S FET Qt is formed, and at the same time, a conductor 15 is formed in the connection hole 12 portion to reduce the resistance in the drain region of the n-channel to I S FETQz. do. In addition,
Gate electrode 1 in p-channel MISFET QI
In No. 4, a phosphorus treatment is performed so that the n-type conductivity type is not reversed by impurities introduced into the north region and drain region to be formed in a later step.

After the step 1 shown in FIG. 7, the source region S:
, - and drain regions are introduced, and p-type impurities are introduced into a selected main surface portion of the semiconductor substrate 8 to form a source region S and a drain region. These impurities may be introduced using ion implantation technology. After this, by heat treatment, as shown in FIG. 8, the n-type impurity is stretched and diffused to form an n+ type semiconductor region 16, and the p-type impurity is stretched and diffused to form a p+ type semiconductor region 16. A semiconductor region 17 is formed. The semiconductor region 13 is integrated into a semiconductor region 16 by stretching and diffusing impurities to form a drain region.

After the step shown in FIG. 8, an insulating film 18 made of, for example, phosphosilicate glass (PSG) is formed on the entire surface. After this, the insulating film i1 on the predetermined semiconductor region 16.17.
is is selectively removed to form a connection hole 19 for electrical connection with wiring.

Through this connection hole 19, a predetermined semiconductor region 16° 17° C.
If the wirings 20, 21, and 22 made of the second conductive layer are formed so as to be electrically connected to the conductive layer, it becomes busy as shown in FIG. 3 and FIG. 8g4.

Through these series of manufacturing steps, the semiconductor integrated circuit device of this embodiment is completed. Note that, after this, a treatment such as a protective film may be applied.

〔effect〕

In semiconductor integrated circuit devices equipped with 0Ml5 consisting of 01 layer main wiring for electrically connecting semiconductor elements, etc., the number of manufacturing steps in the manufacturing process is increased 1-
By providing a conductor layer for one MISFET and providing multiple connection holes for the other MISFET, diffusion in the semiconductor regions constituting each MISFET can be improved without the need for major layout changes. The layer resistance value can be reduced. Therefore, it is possible to improve the operating time of circuit elements configured with 1.0Ml5, and to make it possible to increase the speed of semiconductor integrated circuit devices.

As above, the present invention has been specifically explained based on Examples, but the present invention is not limited to the Examples described above, and various changes can be made without departing from the gist thereof. It goes without saying that there is. For example, although this embodiment has been explained using an inverter circuit, NAND
The present invention can be applied to semiconductor integrated circuit devices configured with various OMI5 circuits, such as EXNOR circuits and EXNOR circuits. Well, the conductivity type of the impurity introduced into each impurity introduction region may be transparent tm.

[Brief explanation of the drawing]

1 and 2 are diagrams for explaining the background art of the present invention, and FIG. 3 is a diagram for explaining the structure of an embodiment of the present invention.
A main part plan view of a semiconductor integrated circuit device equipped with Ml5. The fourth factor is a cross-sectional view taken along the line IV-IV in FIG. 3. FIGS. FIG. 3 is a cross-sectional view of a main part of a semiconductor integrated circuit device equipped with an OMIS in each manufacturing process for explaining a manufacturing method. In the figure, 8... semiconductor substrate, 9... well region, 10
...Field insulating film, 12.19...Connection hole, 1
1゜18...Insulating film, 13,16.17...Semiconductor region, 14...Gate electrode, 15...Conductor, 20
~22...Wiring, Q+ -Q-...MISFET,
S...source region, D...drain region, CI~0
τ゛゛It is a connection hole. Figure 1 Ver. Figure 2 Figure 3

Claims (1)

[Claims] 1. A first insulated gate field effect transistor having a gate electrode constituted by a first conductive layer and a first conductivity type semiconductor region used as a source region and a drain region; In a semiconductor integrated circuit device comprising a second insulated gate field effect transistor having a semiconductor region of two conductivity types, the semiconductor integrated circuit device has as much contact surface as possible with one semiconductor region of the first insulated gate m field effect transistor. A first wiring constituted by a second conductive layer provided in electrical connection and having as much contact surface as possible on the semiconductor region of one of the second insulated gate field effect transistors. A conductor constituted by a first conductive layer provided, and a second conductive layer provided electrically connected to one semiconductor region of the second insulated gate field effect transistor or the conductor. 1. A semiconductor integrated circuit device comprising: 2. The semiconductor integrated circuit device according to claim 1, wherein the electrical connection between the first wiring and the semiconductor region is formed by a plurality of connection holes.