JPS603703B2 - semiconductor memory - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a structure of a memory array in a semiconductor memory.

Memory that produces one bit with one slave transistor,
For example, MOS (Metal-○ illusion de-Semic-
1 and 2 are used in the memory. In other words, in FIG. 1, when reading out a memory cell MCo, for example, a word line Wo and a circuit belonging to another data line Do are used. A pulse is simultaneously applied to the dummy word line DW, and the minute signal output appearing on the two data lines Do is used as a read signal from the memory cells MCo and DM, and the set signal Set of the preamplifier PAo is turned on. Preamble PAo by
was operated and amplified, and the tortoise pressure appearing on either the Do or Do data line was detected to discriminate between information "1" and "0".

The reason why differential signal output is generated here is as follows. The voltage stored in the capacitor Co of the dummy cell DM is the information “1” and “0” stored in the memory cell Co.
Since the voltage that appears on the data line from reading the dummy cell is set to approximately the middle of the voltage corresponding to "1" of the memory cell. This is approximately the middle of the data line voltage when reading "0". Therefore, the difference between this intermediate value and the "1" and "0" outputs becomes the difference signal output with different polarity.

Figure 2 is a schematic diagram of a circuit that takes into consideration the geometrical arrangement when multiple circuits shown in Figure 1 (e.g., mice here) are implemented on one chip to form one memory. be.

In the figure, the white circles are memory cells, and the black circles are dummy cells.
For example, in order to extract the signal appearing on the data line Do to the outside as described above, turn on the transistor Qo according to the address signal, input the signal on the data line ○o to the main amplifier MA and amplify it, and then It is taken out from the chip as the output Do pile. Now, the disadvantages of such a configuration are as follows. In other words, ■Data lines Do, D
Main amplifier M outputs only one side of the lid movement signal that appears at
Since it is amplified by A, it is inferior in terms of high speed. (2) Since one signal is taken out, electrical imbalance between Do and Do tends to occur, causing malfunction.

■The data lines Do, Do whose electrical characteristics should be balanced are
D due to lack of geometrical proximity within the chip. ,D.
unbalanced noise is likely to couple with the preamplifier, causing malfunction when the preamplifier is turned on. Due to these deficiencies, there has been a limit to the design of high-speed, highly stable BI closing molyies. Therefore, one object of the present invention is to provide a semiconductor memory that has a large noise margin and can be highly integrated. Z For this reason, one embodiment of the present invention proposes ``In a dynamic random access memory in which adjacent data lines are read out as a pair, a line connecting the contact portion of the diffusion layer and the center of the capacitor, that is, the By running a word line in a direction perpendicular to the channel length direction 2 and using the word line itself as a control electrode, that is, a gate, of the access transistor, a highly integrated layout that is resistant to noise is made possible. This will be explained in detail in the following 2 embodiments. Fig. 3 shows an example of the circuit.

That is, the data line pair Do, where differential read signals appear,
Do are arranged close to each other in parallel as shown in the figure, and one each of the word lines (Wo to W63, DWo, DW,) and Do
, Do, a memory cell is connected to only one of the intersections. When reading a certain memory cell (for example, MC63), the data line (0
. ) are simultaneously read out, and the differential voltage appearing on the data lines Do, o is effectively used for the preamplifier P. Also preamplifier PAo
The amplified differential signal is input to the differential amplifier MA through transistors Qo and Qo by the input 0 of the address signal Ao, which is the output of the decoder, and is differentially amplified again. In this way, in the present invention, D is completely different from the case of FIG.
The electrical balance of o and Do is not disturbed in any way. FIG. 4 is a schematic diagram of the subsequent method (8-pit memory cell) while maintaining the electrical balance of Do and Do. In the figure, a, b, and c are methods of connecting memory cells to Do and Do every every other, every second, and every fourth memory cell, respectively. Figures 5a and 6 are shown in Figure 4b using a silicon gate process.
, c is an example of a layout. FIG. 5b is a cross-sectional view of section AA' in FIG. 5a. In the figure, a storage capacitor forming electrode cp made of polysilicon is for forming a storage capacitor Co in a memory cell as shown in FIG. 400, 41 are formed within the silicon substrate 600,
A drain and a source (or a source and a drain) for forming the transistor Q, and 420 corresponds to 410 and are a drain (or source) for forming Co.

The storage capacitor forming electrode Cp, word line W59, etc. are made of polysilicon, and the data lines D, etc. are made of aluminum. Data line D, etc. and word line W59
etc. are separated from the insulating film 2001. 10 is a contact portion between the data lines Do, Do, etc. and the diffusion layer 400.

In N-channel MOS, the storage capacity Co is formed by c
When a high voltage is applied to p, the capacitance between cp and the channel formed directly below becomes Co.

To briefly explain the operation using FIG. 5, when a pulse voltage is applied to the word line, for example, W6o, the transistor Q (
(corresponding to Q in MCo in FIG. 1) is turned on, and the storage voltage of Co becomes D, which is divided by the capacitance of data line Do and Co.
A voltage will appear. On the other hand, since the transistor Q does not exist on the data line Do that is paired with this,
No output appears. The output appearing at Do is only the output from the dummy cell (not shown), as described above. As is clear from FIG. 5, the distance between the diffusion eyebrows of the contact portions Do and D can be made large because the AI wiring is present in the middle. Therefore, there is an advantage that punch-through between Do and D can be avoided. Another advantage of FIG. 8 is that the layout of the preamplifier PAo is easier than before. In other words, in the conventional Figures 1 and 2, between Do and Do, which are laid out in a straight line with each other, P, which occupies a much larger area than the memory cell and has a more complex circuit configuration, must be laid out. Not necessarily,
It was extremely difficult to consider the pitch of the data lines. However, in FIG. 3, there is a layout area that is approximately twice as large as the conventional layout with respect to the data line pitch, making the layout extremely easy. Further, the preamplifier PAo may be placed on the MA side as shown in FIG. 3, or on the edge of the pond above Do and Do (W63 side). W6
By arranging P on the third side, as shown in FIG. 3, control circuits whose layout is relatively difficult (P, Qo, etc.) are not concentrated only at one end. Depending on the case, preamplifiers may be arranged alternately on the MA side and the W63 side on the data line. As described above, according to the present invention, the degree of freedom in layout can be greatly increased. Further, although FIGS. 5 and 6 show examples in which the word lines are polySj, the same layout is possible even when the word lines are AI, and the same applies to the case of AI gates.

In addition, in this example, one bit is configured with one transistor, but in order to extract signals differentially from the data pair lines, a memory cell is connected only to one of the two intersections with the word line, and It is clear that the concept shown in FIGS. 3 and 4 using dummy cells can be applied to all memory BIs.

In FIG. 3, CD and CD are common data lines for writing and outputting data. From the above, it is possible to realize a memory BI with high speed and highly stable operation.

[Brief Description of the Drawings] Figures 1 and 2 show a conventional memory configuration in which one bit is configured with one transistor, and Figure 3 shows an implementation of the present invention in which a read signal is output from only one side of a data pair. For example, FIG. 4 shows a memory cell connection method, and FIGS. 5 and 6 show layout examples using Si gates. Do, Do, D,: data line, Wo...W62: word line, DWo, DW,: dummy cell word line, MC
6, MC,: memory cell, DMo, DM,: dummy cell, Co: storage capacity, transistor in Q memory cell, WD
:Word driver, Q〇,Q. ~Q3: Data line selection transistor, ~A63: Address signal, PAo~PA63: Preamplifier, MA: Main amplifier, Set: Set signal, CP: Co formation electrode. Figure 2 Figure 1 Figure 3 Figure 4 Figure 5 Figure 6

Claims (1)

[Claims] 1 A plurality of semiconductor memory cells, a word line extending in the vertical direction and a data line extending in the horizontal direction electrically coupled to each memory cell, and two of the data lines forming a pair. ,
In a semiconductor memory having a sense amplifier coupled to the data of the pair and reading a storage signal of the memory cell appearing on the other data line with reference to the potential of one data line, the data lines of the pair are parallel to each other. The word line itself constitutes a control electrode of the switch means in the memory cell, and the direction of current in the switch means is arranged substantially perpendicular to the running direction of the word line. A semiconductor memory characterized by: