JPS604341A - Receiving circuit of spectrum spread communication system - Google Patents

Abstract

PURPOSE:To improve the reliability of a receiving circuit by sampling the output signal of a correlating circuit in the center position of a peak of this output signal surely and easily to demodulate a data signal accurately. CONSTITUTION:A base band signal, where a carrier is eliminated from a received signal by a circuit means which is not shown in a figure, is inputted to a correlating circuit 11, and correlations between this base band signal and a PN code are operated, and transfer clocks are counted by a ring counter 16. The second latch circuit 17b latches a synchronizing timing, and the first and the third latch circuits 17a and 17c latch timings before and after the synchronizing timing. The output of the ring counter 16 and outputs of latch circuits are compared by respective comparators. The second and the third sampling circuits sample the output of the correlating circuit 11 by outputs of the first and the third comparing circuits 18a and 18c. The oscillation frequency of a VCO22 is changed in response to the output of a difference circuit 20 which operates the difference between outputs of the second and the third sampling circuits, and the output is given as the transfer clock to the correlating circuit 11, and the transfer clock is allowed to follow up the clock of a spectrum spread signal.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a receiving circuit in a digital communication system, particularly a spread spectrum communication system.

<Prior art and its problems> A spread spectrum signal S(t) as a transmission signal in spread spectrum communication is a data signal d(t)(
A binary time series signal of value (d+1 or 1).

PN, (pseudorandom noise) code as p(t) (value +1
Alternatively, if the carrier wave is coθωct, it is expressed by the following equation (1).

5(t) = d(t) P(t)Cosωct...
(1) However, ωc = 2πfc fC is the carrier wave frequency On the receiving side, this spread spectrum signal S (t) is received as a multiplied signal S (t), and this received signal S (t)
It is necessary to demodulate the theta Shingetsu d (t). Therefore, as shown in FIG. 1, the conventional spectrum communication receiving circuit regenerates the carrier wave coeωct from the received signal S (t), and combines this regenerated carrier wave cosωct with the received signal S (
t) and mixed with mixer 1 to form the spread signal a(t)・p
(t), and the correlation circuit 2 calculates the correlation between the signals a (t), p (t) and the PNN code (1) of the same type as that on the transmitting side.
A method has been proposed in which the data signal a (t) is demodulated by inputting the output signal SA of the correlation circuit 2 to the data cutting circuit 3. The principle of this demodulation is that the output signal SA of the correlation circuit 2 is the data signal d as shown in FIG.
Since there is a peak that becomes positive or negative depending on +1°-1 of (t), this is appropriately determined using threshold values +M and -M (threshold levels) to demodulate the data. By the way, the output signal sA of the correlation circuit 2 has a peak of the data signal a (t) at a certain period, but due to the influence of noise, it may have a peak at a location other than the tail signal a (t). . Therefore, in the conventional receiver circuit shown in FIG. 1, the output levels +M, -
If M is exceeded, there is a risk that a significant amount of the data signal a (t) may be mistakenly determined as a data signal. In order to eliminate such a fear, there is a constraint that the threshold level must always be maintained at an optimal value. To improve this, the output signal SA
It is preferable to judge whether the output signal sA is positive or negative at the center of the peak of
Due to the subtle difference with the code period, the peak is accompanied by a slight time fluctuation (jitter), which makes it difficult to sample accurately at the center of the peak.

<Object of the Invention> The present invention makes it possible to reliably and easily sample at the center position of the peak of the output signal of the correlation circuit, thereby accurately demodulating the data signal and increasing the reliability of the receiving circuit. The purpose is to

<Configuration and Effects of the Invention> In order to achieve the above object, the present invention uses a differential circuit to correct the difference when a difference occurs between the transfer lock of the correlation circuit and the clock speed of the received spread spectrum signal. is detected, and in response to this detection, the oscillation frequency of the VCO is controlled so that the transfer lock, which is the output of this oscillation frequency, follows the clock of the spread spectrum signal. Therefore, according to the present invention, it is possible to reliably sample one point at the center of the peak of the output signal of the correlation circuit, and even if a peak occurs in the output signal other than the data signal due to noise, this peak can be ignored. As a result, the data signal can be accurately demodulated with high reliability without having to maintain the threshold level value for determining whether the peak of the output signal of the correlation circuit is positive or negative. Can provide receiving circuit.

<Description of Embodiments> FIG. 3 is a circuit diagram of a receiving circuit in a spread spectrum communication system according to an embodiment of the present invention, and FIG. 4 is a time chart of signals of each part of the receiving circuit shown in FIG. 3. be.

In FIG. 3, reference numeral 11 is a correlation circuit. This correlation circuit 11 has received signal 5(t) [= d(t) P
(t) CosωC°C], the carrier wave cosωct is removed by a circuit means not shown, and the signal d(°C)P(t), which becomes a baseband signal, is input. This correlation circuit 11 includes an analog not register 11a and a PN code register 11b which transfer and lock a signal SB, which will be described later.
It includes a plurality of mixers 11c, 1lc- for each bit of both registers 11a, llb, and a combiner 11a. At the output section of the correlation circuit 11, an output signal SA as shown in FIG. 4 (2L) K appears. Analog knot register 11aK
is a tapped delay line, CCD (Charge
Coupled Device), BBD (
Buc-4<et Brigate Device)
is used. 12 is an analog comparison circuit, and a voltage corresponding to the negative phase (1111 human power section - KU threshold level M) of this analog comparison circuit 12 is applied,
The output signal SA of the correlation circuit 11 is connected to the input terminal 10 on the positive phase side.
is given. 13 is a knot circuit, and 14 is a group of flip-flops. Flip-flop group 141-1', first
．． Second. Third flip-flop 14a, 141), 14
Consists of C. 15 is an AND circuit, 16 is a ring counter, and 17 is a latch circuit group. The latch circuit group 17 is the first
．． Second. From the third latch circuits 17a, 17b, and 17C. 18 is a digital comparison circuit group, and this digital comparison circuit group 18 is connected to the first . Second. Third digital comparison circuit 18
5, 113b, and 18C. 19 is a sample and hold circuit group, and this sample and hold circuit group 19
is the first. 2nd and 3rd sample and hold circuits 19a, 19
b, consisting of 19C. 20 is a difference circuit, and this difference circuit 20 has a subtraction circuit 20a and a multiplication circuit 20b. 21 is a low-pass filter, and 22 is a UVCO (voltage controlled oscillator).

Next, the operation will be explained with reference to the time chart of FIG. 4, and the functions of each of the above-mentioned circuits will also be explained. First, the transmitting side must select []” or “O” at the beginning of the transmission operation.
The first bit is "
1".

In the receiving circuit of FIG. 3, a start signal Sc shown in FIG. 4(C) is applied to the reset terminal of the flip-flop group 14 to set each of the flip-flops 14a to 14C as a reset terminal. Based on the above assumption, at the start of transmission, the data is
1'', the output signal sA of the correlation circuit 11 is
As shown in Figure (a) K, there is a sharp peak on the positive side. The analog comparison circuit 12 compares the level of the output signal SA with a threshold level M, and when the output signal SA exceeds this level M, the comparison circuit 12 detects a peak as shown in FIG. 4(d). A signal SrI is output. This peak detection signal StD is generated by the knot circuit 1.
3 to the cent terminal S of the first flip-flop log 14a.
given to. As a result, the first flip-flop log 14
a is set, and with this seven soto output, the second. The 37th lip flops 14b and 14C are both set.

In this way, a signal SE as shown in FIG. At this time, the oscillation output signal SR of the vco 22 is applied to the other input section of the ant circuit 15 and the ring counter 16. The output signals S and B of this oscillation are shown in FIG. 4(1)). Then, this ring counter 16 receives this output signal.
It is counted up by the code SB, and its counting cycle matches the cycle of the PN code. Further, the count value of the ring counter 16 is latched in the first to third launch circuits 17a to 17C via the AND circuit 15. Then, the output signal SE is as shown in Fig. 4(b) (e).
As shown in the figure, the count timing changes from "1" to "0".
It has become.

At this time, the counter contents of the ring counter 16 at the count timing (3) are loaded into the first latch circuit 17a, and the counter contents of the ring counter 16 at the count timing (2) are loaded into the first latch circuit 17a. The counts and contents at count timings ① and ② are launched in the third latch circuits 171) and 17C, respectively. Here, count timing ■ is the fourth
As shown in Figures (a) and (b), the timings are synchronous with Nakagami, and the count timings ■ and ■ are each one clock timing before and after the center timing ■.

If the PN code on the transmitting side and the transfer lock SB on the receiving side are completely synchronized, the central count timing ■
The output signal SA of the correlation circuit 11 is sampled by the first sample and hold circuit 19a, and the data signal can be demodulated by determining whether it is positive or negative. However, if the above synchronization is out of sync, for example as shown in Figure 4, the transfer lock
If B is faster than the PN code speed on the transmitting side, the count timing ■■■ will be temporally shifted earlier than the peak of the output signal SA of the correlation circuit 11.

At this time, the output of the ring counter 16 and the
The stones launched by the launch circuits 17a to 17C and the count values corresponding to each count timing are compared by the first to third comparison circuits 18a to 18C, respectively. The first comparison signal S H of the first comparison circuit 18a is shown in FIG. 4(k), and the second comparison signal S F of the second comparison circuit 18'b is shown in FIG. The third comparison signal SG is the fourth
Each is shown in Figure (j).

The first comparison signal SH corresponds to count timing ■, the second comparison signal SF corresponds to count timing ■, and the third comparison signal SH corresponds to count timing ■.
The comparison signal SC corresponds to count timing ■. Second
The comparison signal SF is given as a sample signal to the first sample-and-hold circuit 19a, whereby the output signal SA of the correlation circuit 11 is sampled and the data signal a (t) is demodulated. The third comparison signals Sr-+ and Sc are supplied to the second and third sample-and-hold circuits 19b and 19, respectively.
C as a sample signal, and the output signal SA
sample. Here, each comparison signal SH, SF.

In SG, the output of the ring counter 16 is connected to each latch circuit 17a.
This is a signal that becomes "L" when it matches the output of 17C, and has an interval of every other clock of the clock signal SB.

Second. Third sample and hold circuit 191), 19C
The output signals Sb and Sa of the subtracter 20a of the difference circuit 20 are
is subtracted by This subtraction output signal Sc is multiplied by the output signal SJ of the first sample-and-hold circuit 19a shown in FIG. 4(m) by a multiplier 201). Multiplier 20
As shown in FIG. 4(1), the output signal 81 in step 1) becomes negative because the clock signal sB is faster than the PN code on the transmitting side. This output signal 5Itd is inputted to vCO 22 via low-pass filter 21. In this case, the output signal S
Since l is negative, the clock signal SB is slow. Conversely, when the clock signal SB is slower than the PN code on the transmitting side, the clock signal SB becomes faster. In this way, the receiving circuit of this embodiment always uses the clock on the receiving side as the clock on the transmitting side.
It operates so as to be tuned to the frequency of the N code, so that the second comparison signal SF can always be brought to the peak center of the output signal SA of the correlation circuit 11, and accurate demodulation of the data signal can be performed. Note that the multiplier 20b is for dealing with the case where the data is negative.

[Brief explanation of the drawing]

Fig. 1 is a circuit diagram of a conventional example of a spread spectrum communication system, Fig. 2 is a time chart of the output signal of the correlation circuit shown in Fig. 1 and a demodulated data signal, and Fig. 3 is an embodiment of the present invention. The example circuit diagram, FIG. 4, is a time chart of signals of each part of the circuit shown in FIG. 3. 11. Correlation circuit, 12. Comparison circuit, 14. Flip-flop group, 15. Ant circuit, 16. Ring counter, 17. Launch circuit group, 18. Comparison circuit group, 19.
Sample/hold circuit group, 20...Differential circuit, 21...
・Low pass filter, 22...VCO8 Applicant: Tateishi Electric Co., Ltd. Agent: Kazuhide Okada, patent attorney

Claims (1)

[Claims] (1) A correlation circuit that correlates the received spread spectrum signal and the PN code, a ring counter that counts the transfer lock of the correlation circuit, a second latch circuit that latches the synchronization timing, and a The first step is to latch the timing. The third latch circuit, the output of the ring counter, and the first latch circuit. Second. The first latch circuit compares the output of the third latch circuit with the output of the third latch circuit. Second. a third comparison circuit; Third
2. The output of the correlation circuit is sampled by the output of the comparison circuit. a third sample circuit; a difference circuit that takes the difference between the outputs of the third sample circuit; and a VCO that changes the oscillation frequency in response to the output of the difference circuit and provides the oscillation frequency output to the correlation circuit as the transfer lock;
If there is a difference between the transfer lock and the clock speed of the spread spectrum signal, the differential circuit detects the difference, and in response to the detection, controls the oscillation frequency of the VCO to adjust the transfer lock to the clock speed of the spread spectrum signal. A receiving circuit in a spread spectrum communication system that follows the clock of a spread signal.