JPS6045040A - Formation of thin film pattern - Google Patents

Abstract

PURPOSE:To enable to form fine wiring patterns of Al and the like with good accuracy and in cleanness by a method wherein impurities are doped to the surface of a thin film formed of a selected material by ion implantation and wet- etched, resulting in the formation of a required pattern, and thereafter heat treatment is performed. CONSTITUTION:The thin film made of a selected material is formed on a structure, and an impurity is doped to its surface by ion implantation and wet-etched, resulting in the formation of a required pattern, thereafter heat treatment is performed. For example, Al is formed to a fixed film thickness by the known thin film formation method, ions of As, B, or the like is implanted to this Al film by the known ion implantation. Next, a resist is applied over the entire surface and patterned to a required shape, and the required wiring pattern is formed by wet- etching of the Al film, thereafter 20-min heat treatment is performed at 430 deg.C in nitrogen atmosphere and 20-min heat treatment in hydrogen atmosphere.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for forming a thin film pattern, and more particularly to a method for forming a conductor pattern that can be applied to multilayer wiring in the manufacturing process of LSI, preferably MOS FET integrated circuits.

U1 Technique - AQ is used as the wiring material in LSI, and chemical wet I-etching is used as the etching method. Wet etching of AQ will probably continue to be used in the future because of its simple process, but once the line width of AQ becomes 3 .mu.- or less, it is no longer possible to control the line width by wet etching. That's the big reason.

Hillocks occur. That is,
Conventionally, wiring for LSI, etc., is done by forming a thin film of conductive material such as AQ or AQ-8i by vapor deposition or sputtering, forming a pattern, and then heat-treating it at 400°C to 500°C. (hilLock)
It is known that a phenomenon in which protrusions are formed and the smoothness of the surface is lost occurs. Hillocks are the root cause of disconnections due to electromigration and electrical short terminations between the first conductor layer and the second conductor layer, especially in multilayer wiring, and are a major hindrance to realizing multilayer wiring.

Furthermore, conventionally, metal patterns have been formed by wet etching, or fine patterns cannot be formed by wet etching due to the presence of the hillocks described above and the occurrence of the tooth missing phenomenon.

Recently, in order to form fine wiring patterns with high precision, dry etching processes, such as plasma etching, have been used. This plasma etching is a method in which a chlorine-based gas such as ccQ4 is turned into plasma and reacted with AQ to perform etching. It is true that if etching is performed using this method, the pattern of the AQ wiring can be formed with high precision and neatness. However, it is not possible to prevent the occurrence of hillocks as described above, and furthermore, when AQ is formed in two-layer wiring, the cross section of the first AQ layer becomes an acute angle, resulting in poor coverage of the insulating film between the eyebrows. This has the disadvantage of causing wire breakage during wiring formation.

The object of the present invention has been made in view of two or more points, and is to make it possible to form fine wiring patterns accurately and neatly by adding a simple -C step to sea urchin/soto etching. In particular, in the formation of multi-layer wiring made of All-Illumination, there is no disconnection and thin wiring patterns can be formed precisely and neatly.

1 Makoto.

The structure of the present invention includes a step of forming a thin film made of a selected material on a structure, and a step of applying energy to the surface of the thin film to uniformly form crystal nuclei over the entire surface and cause the nuclei to grow. , a step of wet-etching the thin film to form a predetermined pattern, and a step of heat-treating the patterned thin film. Moreover, the said structure is MQS
Also, the thin film pattern is MO8 type 1 unlister (7) AQ-AQ-8i,
Wiring made of materials such as, especially multilayer wiring.

The present invention will be explained below using specific examples.

To avoid star imbalance, AQ, which is commonly used as a good wiring material in LSI manufacturing technology, is formed to a predetermined thickness using a known thin film forming method.1 For example, high-speed magnetron sputtering or rotation It is preferable to form the film with a thickness of 800× to 1 μm using the type E-gun vapor deposition method.

In this embodiment, it is assumed that the He Q film is formed to have a thickness of 17 zm. Next, ions of elements such as Ar, As, and B are implanted into this AQ film by a known ion implantation method. In this example, As ions are used.

As the conditions for ion implantation, the acceleration is set to 60 K e V.
.

The amount of implantation per unit area is l X I O” dos
It is preferable to set it to e. Also, the ion concentration near the surface (especially within 2000λ from the surface) is 5 X l 0
It is preferable that the number of ions/o& is more than 1 ion, and particularly preferably more than 5 x 10'' ions/an?.Next, after coating the entire surface with resist, this 1 nosist is shaped into a predetermined shape. pattern.

After this patterning, the AQ film is wet-etched using an etching solution (phosphoric acid: sulfuric acid: acetic acid = 3:0.17:0.6) to form a predetermined wiring pattern. Thereafter, as a heat treatment step, for example, at 430°C for 20 minutes in a nitrogen atmosphere and for 20 minutes in a hydrogen atmosphere.
Heat treatment for 1 minute.

Connect the wiring pattern created by the above method to Aρ wiring.
An evaluation was made with a wiring pattern created by a conventional method using wet etching without doping with impurities such as s ions. Photo A in Figure 1.

B is AQ line width 2 μs, C and D are AQ line width 2.75 p
Photographs A and C were taken using the method of this embodiment, and photographs B and D were taken using the conventional method. Also, the photo in Figure 2 is lXl0d.

The wiring pattern is 3 μm wide and formed by wet etching after As ion implantation at 60 keV.

As can be seen from these photographs, the AD and wiring patterned using the method of this example do not exhibit the so-called "missing tooth" phenomenon caused by the occurrence of hillocks5, and the wiring patterns are clean and accurate. Recognize.

Second Embodiment A case will be described in which a two-layer ΔQ wiring is formed by applying the above method.

The AQ line patterned by the above method is used as the first layer, and on top of this, a PSG (phosphosilicate glass) film containing 2 mol% phosphorus is formed as an interlayer insulating film with a thickness of 8000λ.
Provide a thickness of . After this, photolithography and etching for through holes are performed. Then, AQ is deposited on the entire surface to form a second layer of AQ film. Next, this AQ film is patterned and etched into a predetermined shape, and heat treated at 430° C. in a nitrogen and hydrogen atmosphere.

SEM (Scann) of two-layer wiring created using this method
j,ngelecjron I! 1icroscope
) The photo is shown in Figure 3. As you can see from this photo, the patterning of the two-layer AQ wiring is accurate, the coverage is good, and the difference between the wiring is small. Karu.

As can be seen from the following Examples 1 and 2, according to the present invention, hillocks associated with conventional AQ film formation can be prevented;
Furthermore, it is possible to prevent defects such as "missing teeth" that occur with the formation of fine wiring, which was a drawback of wet etching, and furthermore, it is possible to prevent defects caused by dry etching in two-layer wiring technology, which has thin first-layer wiring. It is also possible to prevent defects in the cover registration of the interlayer insulating film during the formation of two-layer wiring.

The reason for this is that the cause of hillocks is that thermal stress received during heat treatment causes anisotropic growth centered on crystal nuclei locally present near the surface. In the present invention, ion implantation is performed before heat treatment.
By adding two layers, crystals are actively formed on the entire surface and anisotropic growth occurs uniformly over the entire surface, thereby suppressing the formation of local hillocks. In other words, AQIII formed by vapor deposition etc. is considered to be non-uniform in terms of its internal structure.If some unrestricted W structure exists locally, especially near the surface, such a structure may be formed during subsequent heat treatment. Hillocks are formed based on local thermal stress generated in non-uniform structural parts! [There is a possibility that In the method of the present invention, first, before heat treatment, 80. IvA is ion-implanted with predetermined ions to make the structural film quality of the All film uniform. The purpose is to actively uniformize the temperature and avoid local concentration of thermal stress during heat treatment. In this example, an ion implantation method conventionally known in semiconductor technology is used as a method of applying energy to the surface of a thin film to generate crystal nuclei and uniformly grow the nuclei over the entire surface. However, the method is not limited to this, and it is also possible to use a general ion implantation method, such as reverse sputtering or plasma treatment.

As a result, it has become possible to prevent such hillocks, and as a result, fine wiring patterns that previously could not be created using wet etching can now be made fine for the first time by actively using wet etching. Wiring patterns can be formed. In other words, it has never been thought to be possible to practically use a process that actively uses etching to form fine patterns.

Furthermore, dry etching has been used to overcome the drawbacks of conventional etching when multilayer wiring is used, and although this has made it possible to form fine patterns, the coverage of the glabella insulating film is not good and wires are easily broken. This drawback can also be solved by the present invention] (For example, wet etching can be actively used, so the drawback of poor cover registration can be solved.
As a result, the coverage is good, and since no hillocks occur, fine wiring patterns can be formed without disconnections.

As described above, the present invention can prevent the occurrence of hillocks, which has been a problem in the past, and (ii) improve the reliability and life of wiring when applied to the manufacture of semiconductor devices. In particular, it has the effect of facilitating the realization of multilayer wiring for LSI. Also, as an interlayer layer in one-layer wiring, p
sc! When etching is used, an extremely smooth coverage can be obtained, and since no unevenness occurs on the etching edge, it is particularly useful for fine pattern formation.
Now it's very advantageous.

Incidentally, the method of the present invention can be applied to the above-mentioned semiconductors! ! , +j neck 'J
"￥ 121, but also - of any composition; two lower d
It goes without saying that it can be used to form a 9:1 or iV film.

[Brief explanation of drawings]

FIGS. 1(A), (C) and 2 are micrographs of the AQ wiring when wet etching was performed after ion implantation according to the present invention, and FIGS. 1(B), (
D) is a microscopic photograph of the AQ wiring when wet etching was performed without ion implantation, and FIG. 3 is an SEM photograph of the AQ two-layer wiring formed according to the present invention. Patent applicant Ricoh Co., Ltd. Figure 1 Figure 3 Question 3 Procedural Amendment Letter January 4, 1981 Commissioner of the Japan Patent Office Kazuo Wakasugi 1%58$1213il=
f Submission 1, Indication of the case 1982 Patent Application No. 153409 2, Title of the invention Thin film pattern forming method 3, Person making the amendment Relationship to the case Patent applicant Gusdag Ding Kant I Address 143 Ota-ku, Tokyo 1-3-6 Nakamagome November 8, 1982 (Date of dispatch: November 29, 1982) 5. Drawings to be amended and "Brief explanation of drawings" column 6, contents of amendment as per attached sheet. 4. Brief explanation of the drawings Figures 1 (A), (C) and 2 show the metallographic structure of At wiring when wet etching was performed after ion implantation according to the present invention. FIGS. 1(B) and 1(D) are microscopic photographs showing the metallographic structure of At wiring when wet etching was performed without ion implantation, and FIG. FIG. 2 is a micrograph showing the metallographic structure of an AI two-layer wiring formed based on the present invention. Figure 1 A Procedural amendment band July 1980] - 0 Display of case Patent application No. 153409 of 1988 2 Name of invention Thin film pattern forming method 3 Person making amendment Relationship to case Patent applicant Address 3-6 Nakamagome-chome, Ota-ku, Tokyo 143 Name (674) Ricoh Co., Ltd. 5 Contents of amendment (1) As per the attached sheet. (2) On page 4 of the specification, lines 9 to 11, "Give energy to create crystal nuclei uniformly over the entire surface and cause nucleus growth" was corrected to "dope with impurities by ion implantation". do. Attachment 2, Claims 1) A step of forming a thin film made of a selected material on the structure, a step of doping impurities into the surface of the thin film by ion implantation, and a step of wet etching the thin film to form a predetermined etched film. 1. A method for forming a thin film pattern, comprising the steps of: forming a pattern; and heat-treating the patterned thin film. 2) In the above item 1, the thin film pattern is MO8
This is the wiring for a type transistor. 3) In the above item 2, the wiring is a multilayer wiring.

Claims (1)

[Claims] ■) A step of forming a thin film made of a selected material on the structure, and a step of applying energy to the surface of the thin film to uniformly form crystal nuclei over the entire surface and cause the nuclei to grow. A method for forming a thin film pattern, comprising the steps of: 1-etching the thin film to form a predetermined pattern; and heat-treating the patterned thin film. 2) In the above item 1, the Wf film pattern is MO
This is the wiring for an 8-type transistor. 3) In the above item 2, the wiring is a multilayer wiring.