JPS6045865A - Information processor - Google Patents

Information processor

Info

Publication number
JPS6045865A
JPS6045865A JP15280283A JP15280283A JPS6045865A JP S6045865 A JPS6045865 A JP S6045865A JP 15280283 A JP15280283 A JP 15280283A JP 15280283 A JP15280283 A JP 15280283A JP S6045865 A JPS6045865 A JP S6045865A
Authority
JP
Japan
Prior art keywords
request signal
controlled
turned
interrupt request
interruption request
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP15280283A
Other languages
Japanese (ja)
Other versions
JPS6359181B2 (en
Inventor
Yoshihiro Eitai
永躰 義博
Toshio Shimada
嶋田 俊雄
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP15280283A priority Critical patent/JPS6045865A/en
Publication of JPS6045865A publication Critical patent/JPS6045865A/en
Publication of JPS6359181B2 publication Critical patent/JPS6359181B2/ja
Granted legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14Handling requests for interconnection or transfer
    • G06F13/20Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/24Handling requests for interconnection or transfer for access to input/output bus using interrupt

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Bus Control (AREA)

Abstract

PURPOSE:To discriminate easily the state of connection of a device to be controlled with no change of an interface for an interruption request, by making use of an interruption request signal line led from the device to be controlled to discriminate the state of connection of said device. CONSTITUTION:When connection information registers 8-10 of devices 2-4 to be controlled are turned on with an electric power supply or a system reset signal, the interruption request signal lines 5-7 are energized via OR circuits 14- 16 to inform a controller 1 that the devices 2-4 are connected. The controller checks an interruption request signal and transmits a specific instruction to the devices to be controlled when the check is over to reset connection information registers 8-10. These registers are set only by the power supply ON or the system reset signal and therefore never turned on unless the power supply is turned on or the system is reset. Therefore the subsequent interruption signal lines 5-7 can be used as normal interruption request signal lines.

Description

【発明の詳細な説明】 (a)発明の対象 本発明は情報処理装置に係り、特にハードウェア的に分
割された回路又は装置の接続状態を判定する方法に関す
る。
DETAILED DESCRIPTION OF THE INVENTION (a) Object of the Invention The present invention relates to an information processing device, and particularly to a method for determining the connection state of hardware-divided circuits or devices.

(b)従来技術 従来の接続装置の判定方式として i)ザービスプロセソサー又は直接キーにょって情報処
理装置内の特定の記録回路にフラグを設定すると言った
人手によって接続情報を設定する方式 ii )制御装置から被制御装置にアクセス要求を出し
て所定の時間が経過しても応答信号が帰ってこない(い
わゆるタイムアウト)ことによって未接続であることを
制御装置が認識する方法に対する保証方法に問題があっ
た。ii)の方式では所定時間待たねばならず特に未接
続回路が多くなる程時間がかかると言った欠点があった
(b) Prior Art Conventional methods for determining connection devices include: i) A method of manually setting connection information by setting a flag in a specific recording circuit within the information processing device using a service processor or a direct key; ii) ) There is a problem with the guarantee method for the method in which the control device recognizes that there is no connection when the control device issues an access request to the controlled device and no response signal is returned even after a predetermined period of time has elapsed (so-called timeout). was there. The method ii) has the disadvantage that it requires waiting for a predetermined period of time, and the longer the number of unconnected circuits increases.

(c)本発明の目的 本発明の目的は制御装置と複数の被i1i+制御装置と
で構成される情報処理装置において、制御装置によって
制御されるために設けられた複数の被制御装置又は回路
からの割込み要求信号インクフェースをそのまま変更せ
ずに利用して被制御装置の接続状態を判別する方式を提
供することにある。
(c) Object of the present invention The object of the present invention is to provide an information processing device including a control device and a plurality of i1i+ controlled devices, in which a plurality of controlled devices or circuits provided to be controlled by the control device An object of the present invention is to provide a method for determining the connection state of a controlled device by using the interrupt request signal ink face without changing it.

(d)本発明の要点 本発明は被制御装置からの割込み要求信号線を、被制御
装置の接続状態の判別に利用するために、装置の電源O
N又はシステムリセット等によってONとし該別込み要
求信号を制御装置が認識した7多OF Fとなるように
制御することによって従来の割込み要求のためのインタ
フェースを変更せずに容易に被制御装置の接続状態を判
別できるようにしたものである。
(d) Main points of the present invention The present invention utilizes an interrupt request signal line from a controlled device to determine the connection state of the controlled device.
By controlling the separate request signal to be turned ON by N or system reset, etc. so that it becomes 7 OFF, which is recognized by the control device, it is possible to easily control the controlled device without changing the conventional interface for interrupt requests. This allows you to determine the connection status.

(e)発明の実施例 第1図が本発明の一実施例であって1は制御装置、2〜
4は被制御装置、5〜7ば被制御装置からの制御装置に
対する割込み要求信号線、8〜10ば被制御装置2〜4
の制御装置1に対する接続状態を示す接続情報レジスタ
、11〜13は被制御装置における稲常の割込み要求信
号線、14〜16は論理和回路であって、上記通常の割
込み要求信号線11〜13と上記接続状態レジスタ8〜
lOの出力との論理和出力を上記割込み要求信号線5〜
7に接続する。
(e) Embodiment of the invention FIG. 1 shows an embodiment of the invention, in which 1 is a control device, 2 to
4 is a controlled device, 5 to 7 are interrupt request signal lines from the controlled device to the control device, and 8 to 10 are controlled devices 2 to 4.
11 to 13 are Inatsune interrupt request signal lines in the controlled device, and 14 to 16 are OR circuits, which are connected to the normal interrupt request signal lines 11 to 13. and the connection status register 8~
The logical OR output with the output of lO is sent to the interrupt request signal line 5~
Connect to 7.

金波制御装置の接続情報レジスタ8〜1oが電源オン又
はシステムリセット信号によってONとなると上記論理
和回路14〜16を経由して割込み要求信号線5〜7が
付勢され制御装置に対して夫々の被制御装置が接続され
ていることを通知する。
When the connection information registers 8 to 1o of the gold wave control device are turned on by power-on or a system reset signal, the interrupt request signal lines 5 to 7 are energized via the OR circuits 14 to 16, and the respective signals are sent to the control device. Notify that the controlled device is connected.

制御装置側でこの割込め要求信号のチェックを行い終了
したとき直ちに上記接続情報レジスタ8〜10をリセッ
トするために例えば特定の命令を被制御装置に送出する
(ルートは図示せず)と被制御装置側で該命令が受信さ
れて上記接続情報レジスタがリセットされる。
When the control device side checks this interrupt request signal and immediately resets the connection information registers 8 to 10, it sends, for example, a specific command to the controlled device (route not shown). The device side receives the command and resets the connection information register.

この接続情報レジスタ8〜10はそのセット条件が前述
の電源ON又はシステムリセット信号によるだけモある
ので、電源Q、N又はシステムリセットが行われない限
り再びONになることばないので以降の割込み要求信号
線8〜10は通常の割込み要求信号線として使用できる
The connection information registers 8 to 10 are set only by the above-mentioned power ON or system reset signal, so they will not be turned ON again unless the power supply Q, N or system reset is performed, so subsequent interrupt request signals Lines 8-10 can be used as normal interrupt request signal lines.

該レジスタ8〜10のリセット方法については、前述の
ような制御装置からの命令によるだけでなく、制御装置
1が割込み要求信号線5〜7を通して該信号の認識が完
了すれば直ちにリセットできるようにハードウェアで構
成しても良い。
The registers 8 to 10 can be reset not only by instructions from the control device as described above, but also by the method of resetting them immediately after the control device 1 completes recognition of the signals through the interrupt request signal lines 5 to 7. It may be configured by hardware.

以上の説明から明らかなように、制御装置1は該別込め
要求信号を被制御装置の接続状態を判別する信号と通常
の割込み要求信号とに切分けて識別制御する必要がある
が、その手段そのものは本発明の主旨とは直接関係ない
のでここでは省略する。
As is clear from the above explanation, the control device 1 needs to separate and control the separate request signal into a signal for determining the connection state of the controlled device and a normal interrupt request signal. Since it is not directly related to the gist of the present invention, it will be omitted here.

面別込み要求信号のインタフェースについて本発明でば
1:1の割込み要求信号線としているが、本発明の適用
範囲がこれに限定されないことは言う迄もない。
In the present invention, a 1:1 interrupt request signal line is used as an interface for a per-plane request signal, but it goes without saying that the scope of application of the present invention is not limited to this.

(f)発明の効果 本発明によれば、制御装置で特定の割込み処理を行うだ
けで被制御装置又は回路の接続状態を判別できるので情
報処理の高速化、高信頼化に効果がある。
(f) Effects of the Invention According to the present invention, the connection state of a controlled device or circuit can be determined simply by performing specific interrupt processing in the control device, which is effective in increasing the speed and reliability of information processing.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の一実施例を説明する図である。 図において1は制御装置、2〜4は被制御装置。 5〜7は割込み要求信号線、8〜10ば接続情報レジス
タを示す。
FIG. 1 is a diagram illustrating an embodiment of the present invention. In the figure, 1 is a control device, and 2 to 4 are controlled devices. 5 to 7 indicate interrupt request signal lines, and 8 to 10 indicate connection information registers.

Claims (1)

【特許請求の範囲】[Claims] 制御装置と該制御装置によって制御されるためにおいて
、前記割込め要求信号を電源ONまたはシステムリセッ
ト時にONにし、その割込み要求信号を制御装置が認識
した後に’OF Fとして以降通常の割込み要求ができ
るように前記割込み要求信号を制御することを特徴上す
る情報処理装置。
In order to be controlled by a control device and the control device, the interrupt request signal is turned ON when the power is turned on or the system is reset, and after the control device recognizes the interrupt request signal, it is turned OFF and thereafter a normal interrupt request can be made. An information processing device characterized in that the interrupt request signal is controlled so as to control the interrupt request signal.
JP15280283A 1983-08-22 1983-08-22 Information processor Granted JPS6045865A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15280283A JPS6045865A (en) 1983-08-22 1983-08-22 Information processor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15280283A JPS6045865A (en) 1983-08-22 1983-08-22 Information processor

Publications (2)

Publication Number Publication Date
JPS6045865A true JPS6045865A (en) 1985-03-12
JPS6359181B2 JPS6359181B2 (en) 1988-11-18

Family

ID=15548471

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15280283A Granted JPS6045865A (en) 1983-08-22 1983-08-22 Information processor

Country Status (1)

Country Link
JP (1) JPS6045865A (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS56145412A (en) * 1980-04-14 1981-11-12 Hitachi Ltd Interruption signal receiving circuit

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS56145412A (en) * 1980-04-14 1981-11-12 Hitachi Ltd Interruption signal receiving circuit

Also Published As

Publication number Publication date
JPS6359181B2 (en) 1988-11-18

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