JPS6047509A - Attenuating circuit - Google Patents

Abstract

PURPOSE:To obtain a circuit with low power consumption while preventing distortion due to nonlinearity by arranging an NPN and a PNP type transistor (TR) at both terminals of voltage dividing resistances, and setting a damping factor regardless of the nonlinear impedance at the terminal parts of the voltage dividing resistances. CONSTITUTION:An attenuating circuit is constituted by combining the PNP type TRQ1 and PNP type Q2, and voltage dividing resistances R1 and R2 arranged between the TRs Q1 and Q2. The base of the Q1 is regarded as a signal input terminal 1 and impressed with a signal VIN, and the connection point between the R1 and R2 is used as a signal output terminal 2 to lead out a signal VOUT. Then, the output impedance characteristics of the TRs Q1 and Q2 become nonlinear. Then when equal emitter currents are flowed through the TRQ1 and Q2 and R1=R2, nonlinear distortion is canceled by the damping factor.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to an attenuation circuit, and more particularly to an attenuation circuit having a circuit configuration with low distortion by removing nonlinear elements.

[Technical background of the invention and its problems] Generally, a voltage dividing circuit using resistors is used as an attenuation circuit. As shown in Fig. 1, the conventional attenuation circuit is composed of an emitter follower circuit in which the base is the signal input terminal 1, the collector is connected to the DC power supply, and the emitter is grounded through the voltage dividing resistors R+ and R2. The connection point between and R2 is the signal output end 2. When looking at this circuit from the output side, if the output impedance of the emitter follower is -1'j lb, then as shown in Figure 2, between the signal input terminal 1 and the ground, there is an impedance aib, a resistor R+,
R2 are connected in series, and the input signal VIN supplied to the signal input terminal 1 is voltage-divided and taken out from the signal output terminal 2 as the output signal VOIJT. In this case, the attenuation rate G is given by: G=R2/(R1+R2+dLb) (1). Output impedance A L shown in equation (1)
b is a nonlinear term, and the nonlinearity of this output impedance ilb causes distortion in the output signal VOLIT.

In order to reduce this distortion, it is necessary to make the output impedance -It Lb of the emitter follower sufficiently smaller than the voltage dividing resistors R+ and R2. For this reason, a circuit configuration as shown in FIG. 3 can be considered. In FIG. 3, the base is connected to the signal input terminal 1 and the collector is connected to the DC power supply Vcc, and the emitter of the transistor Q1 is connected to the constant current source 11.
On the other hand, the emitter of the transistor Q] is grounded via the voltage dividing resistors R+ and R2, and the connection point between the resistors R+ and R2 is the signal output terminal 2. Here, if the output impedance of the emitter follower is dab and the DC emitter current is Ie, it is given by ALb-(VT/Ie)-(2>.

VT is defined as Vv = 6i T/¥. However, Ω is the absolute temperature, β is the Boltzmann constant, and 7 is the charge of the electron. Therefore, if VT/Ie'CRI +R2-(3), then the output impedance kLb is the voltage dividing resistor R+.

It can be made sufficiently smaller than R2, and distortion due to nonlinearity can be reduced.

In order for the formula (3) to hold true, it is sufficient to cause a large amount of direct current le to flow through the emitter follower, or to make the voltage dividing resistors R1+R2 have high resistance.

However, in the circuit shown in Fig. 3, flowing a large amount of DC current 1e increases power consumption, which is inappropriate for a circuit that requires low power consumption. A high resistance has the disadvantage of deteriorating high frequency characteristics.

[Object of the Invention] In view of the above-mentioned points, the present invention is capable of preventing distortion caused by the nonlinearity of the output impedance in a conventional attenuation circuit using an emitter follower, and furthermore, it is possible to prevent distortion from occurring due to the nonlinearity of the output impedance in a conventional attenuation circuit using an emitter follower. It is an object of the present invention to provide an attenuation circuit that can reduce power consumption and does not increase voltage dividing resistance and deteriorate frequency characteristics.

[Summary of the Invention] The attenuation circuit of the present invention has a first . A second voltage dividing resistor is connected in series, the base of the NPN transistor is used as a signal input terminal, and a second DC power supply is connected to the base of the PNP transistor (or a second signal input terminal is used). ) and the above 1. The connection point of the second voltage dividing resistor is configured to be the signal output terminal.

[Embodiments of the Invention] Hereinafter, embodiments of the present invention will be described based on the drawings.

FIG. 4 is a circuit diagram showing an embodiment of the attenuation circuit according to the present invention, and FIG. 5 is an equivalent circuit diagram as seen from the output side.

As shown in FIG. 4, the attenuation circuit includes an NPN transistor Q1, a PNP transistor Q2, and a transistor Q.
It is constructed by combining voltage dividing resistors R+ and R2 arranged between R+ and R2. NPN transistor Q1
The input signal VIN is supplied by using the base of the signal input terminal 1, and its collector is connected to the DC power supply Vcc, and its emitter is connected to a series circuit of voltage dividing resistors R+ and R2, and this series circuit is a PNP type transistor. connected to the emitter of Q2, its collector is grounded, and its 5
- The base is connected to a DC power source Ve. Then, the connection point between the resistors R1 and R2 is set as the signal output terminal 2, and the output signal V
Taking out nυ■.

In such a configuration, the NPN transistor Q1, PN
Let each output impedance of P-type transistor Q2 be A j
, b+ , k (assuming bz, the equivalent circuit seen from the output side is shown in Figure 5, and the attenuation rate G of this circuit is: G= (R,!15Lb2)/(R1+R2+near ib)
l15Lbz) ...(4) It is given by. In the above equation, dJb+ and dab2 are nonlinear terms, but since the emitter currents of transistors Q+ and Q2 are equal, ■Lb+''5lb2, and R+ =
If R2, then G=1/2. Therefore, in the circuit of Fig. 4, when R+ = R2, the attenuation factor is -6 regardless of the two nonlinear impedances i'tlb+ and dab2.
dB, and nonlinear distortion is canceled at this attenuation rate.

FIG. 6 is a circuit diagram showing another embodiment of the present invention.

6- The attenuation circuit shown in Figure 6 is constructed by adding a resistor R to the circuit shown in Figure 4.
This is a circuit configuration in which a third PNP transistor Q3 is added, and the NPN transistor Q in the circuit shown in FIG.
Voltage dividing resistor R+ on the emitter of 1, resistor R3 in parallel with R2
The other end of the resistor R3 is connected to the emitter of the PNP transistor Q3, its collector is grounded, and its base is connected to the DC power supply Vs together with the base of the PNP transistor Q2.

In such a configuration, NPN transistors Q+, P
Each output impedance of NP type transistor Q2 is dL
b+, 4il)2, the attenuation rate G of this circuit is as in equation (4) above, G= (R2+i'7ib 2 ) / (R1+R2
+dLb++ Fire 1b2) is given. In the above formula, R2/R+ = k
1t)2/-pLLb+, then G=R2/'(R
1→−R2>. Therefore, the attenuation factor G can be determined by appropriately setting the voltage dividing resistance ratio and the output impedance ratio of the transistors Q+ and Q2, that is, the emitter current ratio of each transistor Q+ and Q2.
It is possible to take any value depending only on the values of the resistors R+ and R2, regardless of the near Lb2, and the nonlinear distortion is canceled out at the attenuation rate. However, the set damping rate G
A value of greater than 1/2 and less than 1 is appropriate. In this case, if the emitter currents of transistors Q+ and Q2 are Ie+ and Ie2, respectively, then (R3/(R1+R2
) ) / (R1+R2)=R1/R2, then Ie
+/Ie2yR2/R1, -pLLl)2/5L
b+ yR2/R+. However, R3/ (R1+
R2) is a parallel combined resistance value of the series resistance (R1+R2) and the resistance R3.

FIG. 7 is a circuit diagram showing still another embodiment of the present invention.

The attenuation circuit shown in FIG. 7 is an NPN version of the circuit shown in FIG.
The circuit configuration includes a type transistor Q3 and a resistor R3, and the NPN type transistor Q in the circuit shown in FIG.
An NPN transistor Q3 whose collector is a common collector and whose base is a common base is provided, one end of a resistor R3 is connected to its emitter, and the other end of the resistor R3 is connected in parallel with the voltage dividing resistors R1 and R2. is connected to the emitter of the PNP transistor Q2.

In such a configuration, NPN transistor Q+, PN
PNPN transistor Q2 output impedance dib
+, dib2, the attenuation rate G of this circuit is the above (
Similar to formula 4), G-(R2+-+'jLbz)/(R1+R2+
dll)1+5Lbz). In the above formula, R2/R+=dLb2/
5j, b+, then G=R2/ (R+ 1R2). Therefore, the attenuation factor G is determined by the voltage dividing resistance ratio and the output impedance ratio of transistors Q+ and Q2, that is, each transistor Q1. By appropriately setting the emitter current ratio of Q2, it is possible to take any value depending only on the values of the resistors RI' and R2, regardless of the nonlinear impedance near Lb+ and dLb2, and the nonlinear distortion is canceled at the attenuation rate. . However, the set attenuation rate G is larger than ○ and is 1.
A value smaller than /2 is appropriate. In this case as well, the emitter currents of transistors Q+ and Q2 are respectively Ie+.

If re2, then (R3/ (R1+R2) )/(R
If 1+R2>=R+ /R2, then Ie+/1e2-R
z/Rt, and k Lb 2 / k i, b t
= R2/R+. However, R3/ (R1+
R2) is a parallel combined resistance value of the series resistance (R1+R2) and the resistance R3.

In FIGS. 8 to 10, the DC current m V s of the circuits shown in FIGS. 4, 6, and 7 is removed and a second signal input terminal 3 is provided, and two input signals VINI are provided.

This is a circuit configuration in which V IN 2 is added and output. With this configuration, it is possible to realize a two-person adder with low distortion.

[Effects of the Invention] As described above, according to the present invention, an NPN transistor and a PNP transistor are arranged at both ends of voltage dividing resistors connected in series, and a nonlinear impedance is provided at the ends of both voltage dividing resistors. Since the attenuation factor is set regardless of the two nonlinear impedances, it is possible to prevent distortion based on the nonlinearity of the output impedance, and to reduce power consumption without flowing a large amount of DC current. A power circuit can be configured, and an attenuation circuit with good frequency characteristics can be realized without the need to increase the voltage dividing resistance with respect to nonlinear impedance.

[Brief explanation of drawings]

Fig. 1 is a circuit diagram showing a conventional attenuation circuit, Fig. 2 is an equivalent circuit diagram of the circuit in Fig. 1 viewed from the output side, Fig. 3 is a circuit diagram showing another conventional example, and Fig. 4 is a circuit diagram of the present invention. 5 is an equivalent circuit diagram of the circuit in FIG. 4 viewed from the output side; FIG. 6 is a circuit diagram showing another embodiment of the present invention; FIG. Figure 7 is a circuit diagram showing a further embodiment of the present invention, Figure 8 is a circuit diagram of a two-man powered version of the circuit in Figure 4, and Figure 9 is a circuit diagram showing a further embodiment of the present invention.
This figure is a circuit diagram in which the circuit of FIG. 6 is made into a two-man power type, and FIG. 10 is a circuit diagram in which the circuit in FIG. 7 is made into a two-man power type. 1.3...Signal input terminal 2...Signal output terminal Vcc・
...First DC power supply Va...Second DC power supply Ql...NPN type transistor Q2...PNP type transistor R1...First resistance R2...Second resistance agent
Patent attorney Kensuke Norichika (one idiot) Figure 5 Figure 7 Figure 6 cc Figure 8 cc Figure 9 Figure 10

Claims (1)

[Claims] An NPN transistor whose base is a signal input terminal, whose collector is connected to a first DC power supply, and whose emitter is connected to a first resistor, and whose emitter is connected in series to the first resistor via a second resistor, and whose base is comprises a PNP transistor connected to a second DC power supply and whose collector is grounded, and configured such that a connection point between the first resistor and the second resistor is a signal output terminal. Attenuation circuit.