JPS6055746A - PCM playback device - Google Patents

Abstract

PURPOSE:To reduce noise by outputting information of the preceding frame if a frame pattern is dropped out or many errors occur. CONSTITUTION:If the frame pattern of a synchronizing signal is not detected and correction of the synchronizing signal is not is a correct position or the number of data errors in a frame is very large, contents of memories 11 and 12 to be read out as output data are held as they are memory 11 or 12 of the preceding frame. Since data is outputted from the memory 11 or 12, the noise (shock sound) of the output signal is prevented.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Application) The present invention relates to a PCM playback device, and in particular to an SHF-PCM broadcasting device that prevents the occurrence of noise due to errors.
This invention relates to a PCM playback device that can be used for sin video PCM audio, helical scan tape decks, etc.

(Background) When information is transmitted and received, or when information is recorded over a period of time and then reproduced, the reproduced information may be distorted from the original due to human noise in the transmission or recording medium. The information may not match.

When information is converted into a digital signal, a correction code corresponding to the information is added to the information and transmitted or recorded, thereby correcting error data and faithfully reproducing the information during reproduction.

FIG. 1 shows an example of a signal format for audio PCM transmission. One frame is composed of signals 1 to 5. 1 is a frame pattern that indicates the end of the frame.
2 is a control hood indicating the content of information, 3 is a range bit indicating a scale of information, and 4 is an information signal. information signal 4
is 1 channel to 5 channels (4-1, 4-2,
4-3, 4-4.

There are up to 4-5). 5 is a correction code for error correction.

Figure 2 shows the Pi1 interleave matrix.
There is C. When the one frame is transmitted, it is transmitted vertically in pit units. From the horizontal axis, 7 bits of the correction code are added to the 56 bits of the 1-bit range bit information section code. This pit interleaving disperses burst noise and improves the efficiency of correcting erroneous data.

Furthermore, signals other than the frame pattern are scrambled to facilitate pit black reproduction by the receiver.

Now, the above format is used for the audio information part of broadcasting in the private sector, and is of high quality as PCM audio, but considering the public nature of broadcasting, the C/N in a weak electric field is Even in a degraded state, it is necessary to output reproduced sound.

As described above, the frame pattern is at the beginning of one frame and serves as a reference for reproduction and decoding.

If this frame pattern is not detected, all the information in that l frame cannot be correctly reproduced.

Therefore, the conventional PCM reproducing apparatus has a drawback that noise (shock sound) may be generated in the output signal when a frame pattern is not detected.

(Purpose) The purpose of the present invention is to reduce noise by outputting correctly reproduced mJ frame information when a frame pattern (synchronization signal) is missing or a large amount of errors occur due to long burst noise. The purpose is to provide a playback device.

(Overview) The present invention enables the data of the previous frame to be saved when a large number of errors occur due to non-detection of a frame pattern (synchronization signal) and when a large number of errors occur, or when it is detected that data cannot be corrected. The feature is that the current RAM switching is stopped and the signal of the previous frame is continuously emitted.

Another feature of the present invention is that when a large number of errors that cannot be corrected are detected by the means for detecting errors in the input data, the reproduced data in the frame is replaced with the previous frame 1 sketch data. be.

(Example) The present invention will be explained below by way of examples.

FIG. 3 shows an embodiment of the PCM reproducing device of the present invention.

The data converted into a digital signal is input to a synchronization signal detection circuit 6 and a descrambling circuit 7. The output of the synchronization signal detection circuit 6, which detects the frame pattern as a synchronization signal, activates the descrambling circuit 7. The descrambled data is input to a RAM write circuit 8 for removing bit interleaving.

The RAM is the first RAM prisoner 11 and the second lζA M (B
There are two types, 112, and the write operation and read operation are switched by switch 1o. each RA
M has a capacity for one frame, and in order to solve the bit interleaving as shown in FIG. 2, writing is performed in the vertical direction and reading is performed in the horizontal direction.

Reference numeral 9 denotes a correction circuit, which reads data and detects and corrects erroneous data. 13 is 1ch for each channel
This is an output circuit that separates into ~5 channels.

Now, when no frame pattern is detected by the synchronization detection circuit 6, a pseudo synchronization signal (supplementary synchronization signal) is generated as a reference for system operation.

However, since the start timing of descrambling has been lost, the next RAM switching is stopped.

As a result, the RAM in which erroneous data has been written is not connected to the correction circuit 9. Therefore, in the next frame, S
Writing to the same RAM as the ++ frame and data output from ItAM containing the data of the previous frame are performed.

FIG. 4 shows the waveform of audio information output by the circuit of the above-described embodiment. The output in Fig. 3 is a digital signal, and by passing this through a D/A converter, 24'
i 4 It will look like Figure (a).

In the same figure (al is an example when the synchronization signal of frame number 4 is not detected, and the output of frame number 5 is the data received in frame number 3 two days before. Although there is a lack of continuity, it is possible to avoid the loud shock sounds caused by erroneous data detection.

Furthermore, as shown in the fb1 diagram, it is also possible to perform correction processing at the time of switching between frames ((by doing so, continuity of the signal can be provided).

FIG. 5 is a time chart of the circuit operation of FIG. 3. When the synchronization signal between frame F3 and frame F4 was missing and not detected, the first RAM (4) 11 and the second RAM fB) 12 which were normally switched
Writing and reading operations will stop switching at the next synchronization signal. Therefore, the second RAM (B) 12 performs a write operation again, and the first RAM (4) 11 performs a read operation again. Therefore, frame F4 and frame F
The output data of 5 will be equal.

FIG. 6 shows an example in which output data when a synchronization signal is not detected is distributed and output over two frames. Similarly to the above, when the synchronization signal between frame F3 and frame F4 is lost and cannot be detected, the data in the first RAM (5) 11 is
1 data is output for 2 sample times, and half of the data of one frame is output between each frame. Since the next synchronization signal does not switch the RAM as in the case of the record, the first RAM (A
Similarly, the remaining half of the data of 111 is output every two samples. Therefore, one frame of data is expanded and output over two frames. In the next frame, normal RAM switching is resumed.

In this way, when one frame of data is expanded over two frames, the signal discontinuity as shown in FIG. 4(a) (bl) disappears, and the data becomes close to correct data.

FIG. 7 shows a second embodiment of the present invention in which the gain, tarleave correction, and data output are configured by three RAMs. The circuit configuration is almost the same as that in FIG. 14 is the added third RAMC) 14.

1st RAM prisoner 11. of the second RAM)12. Third R
AM (014) is controlled by the cut-off circuit 15.

The RAM is responsible for three tasks: writing for dinterleaving, detecting and correcting erroneous data, and outputting data. The difference from the above is that the corrected data is not output together with the correction, but the corrected data is rewritten to the original RAM, and an output-only RAM is provided for output.

The switching circuit 15 switches the RAM II in synchronization with the synchronization signal detected by the synchronization signal detection circuit 6.

12.14 is switched by shifting each frame. The connection state of the RAM will be explained with reference to FIG.

In frame F1, the first RAM prisoner 11 is It
The second RAM (B) 12 is connected to the correction circuit 9, and the third RAM (B) 14 is connected to the data output circuit 13. In the next frame F2, cl) RAM hs', t 7) L,,j
, ;13 RAMC) 14 to the RAM write circuit 8,
The first RAM prisoner 11 is connected to the correction circuit 9, and the second RAM (
B) 12 is connected to the data output circuit 13.

Now, if the synchronization signal between frames F2 and F3 is lost, the contents of the second RAMQ3112 become uncertain. Therefore, since the correction in frame F4 is insufficient, and in the next frame F5, the second RAM(B)
12 returns to writing, the first RAM prisoner 11 goes to the correction circuit, and the 33rd RAM M+014 remains as is. Then, the output data of frames F4 and F5 is repeatedly outputted from the third RAM (C114).

Note that this switching control of the RAM can be easily performed by, for example, programming in a ROM or the like.

FIG. 9 shows a method of expanding one frame data into 82 frames and outputting it, as in the previous case. I@3 RAM+01
4 is output across frames F4 and F5.

The above is an explanation of the case where the synchronization signal is missing and the reference point for descrambling becomes unknown, and the data cannot be obtained correctly. Can be read correctly.

Therefore, the third embodiment of the present invention is shown below, in which whether the synchronization signal is detected or not, it is determined whether the data has been correctly observed and the ItAM switching is controlled.
FIG. 10 is an example. This circuit is basically the same as that in FIG. As a result of detecting /- evening errors by the block correction circuit 9, if there are many data errors in the frame, for example, if it is determined that more than half of the data is in error, an abnormality in the frame is recognized and the output is performed. Switch data.

The timing will be explained with reference to FIG. ) Reme F
If there are many errors in the data written in the second RAM () 12 of 3, the correction circuit 9 detects the number of errors in the next frame F4, and when the detection is completed, that is, frame F
4 and frame F5, the RAM switching circuit 1
5, the third RAMC) 14 remains connected to the output circuit, and the first RAMC 11 and the second RAMC (B)
12. As a result, the second RAM (B)
Prevents erroneous υ data output within 12. It goes without saying that one frame data may be expanded into two frames and output as shown in FIG.

Next, another embodiment of the present invention will be described. Figure 11 and m
FIG. 12 shows the relationship between the head and tape of a helical scan type PCM tape deck and the general structure of the PCM tape deck. 16 is magnetic chive,
17 is the trajectory of the recording (or reproducing) head on the tape. One trajectory corresponds to one frame. tape 16
is pulled out from the cassette half 18, and the cylinder 1
It can be wrapped around 9. The surface to be wrapped around is cylinder 19
The angle is approximately 90°. Further, two cylinder heads 20 are provided in the cylinder 19, and each cylinder head 20 is installed at an interval of 180°.

FIG. 13 shows the format of the signal recorded on the tape. One frame is divided into three regions: X, Y, and Z. The Y area is located at the center of the tape and is an area where main data is recorded. Areas X and 2 are located at the end of the tape and are allocated to control data and additional data areas.

The main data area Y shows one block consisting of 256 blocks of θ to 255 by 20V.

Data words in 8-bit units are supplied with a synchronization signal (5YN) from the beginning.
C), control data CC&D).

Data 1, Data 2------D
ata 12, Parity+Parity 2
, Parity 3, Parity 4 r and a 16-bit CRCCJ.

This CRCC is a cyclic code used to detect errors within one block. In addition, data words within a frame are subjected to interleaving (distribution) processing in order to increase data correction efficiency, and the above Parity I 5-Par
ity 4 is similarly interleaved.

Therefore, during playback, % Parity 1 to Parity
In order to correct error data according to No. 4, it is necessary to rearrange the data by dinterleaving the data words and parities within the frame.

Since interleaving is completed in one frame, error propagation due to malfunction of dinterleaving can be completed within one frame.

Now, FIG. 14 shows a circuit according to a fourth embodiment of the present invention. 21 is a CRC check circuit for detecting errors within a block of input data. 22 is a synchronizing signal detection circuit, and 23 is a RAM selection circuit. 24 is a RAM write circuit, 25.26 is a RAM, 27 is a data error correction circuit, and 28.29 is a RAM changeover switch. 30 is a data output circuit, the output of which is transmitted to the D/A circuit.

FIG. 15 is a circuit diagram showing a specific example of the RAM select circuit 23 and the RAM changeover switches 28 and 29.

That is, this circuit can be composed of a T flip-frog 31 and an impatter 32, as surrounded by a broken line. The T flip-flop is toggled by the output of the synchronization signal detection circuit 22 when an abnormally large number of data errors are not detected by the C10 circuit 21. Outputs a low signal. (The output of the C10 circuit 21 is normal, and when the H level is abnormal, it becomes the L level.) When the RAM 25, 26, for example, a high level signal is manually input to its write enable terminal WE, it becomes capable of writing tJJ, and a low level signal is output. When it is input, it becomes readable.

Next, the basic operation of this embodiment will be explained.

As mentioned above, due to the data array format, dinterleaving is required, and two frame RAM
25.20, writing and reading are performed alternately, and dinterleaving is performed by controlling the read address.

The human data is subjected to data error detection by the CRC' check circuit 21, and at the same time, the RAM write circuit 2
4 via fAl's rtAM prisoner 25 or the second RAM (
B) Written to 2G. When the CRC check circuit 21 detects an error in the block, an error flag is added to the data to be penetrated. The correction circuit 27 converts the error data into correct data using the Parity word and the error flag, and outputs the correct data from the data output circuit 30.

Next, the operation of this embodiment will be described in detail with reference to time chart 1 in FIG. The angle of the tape is 90
Since there are two cylinder heads at °, the signal from the tape is one rotation of the cylinder ((head (5) and head (5)).
Two frames of the sum of B) are input.

This intermittent data is alternately written into the first RAM (6) 25 and the second RAM (6) 26.

Now, the time chart time 3 shown in the 16th i'F
When the second RAM (B126) in 1 is damaged, the error flag is abnormal in the output of the CRC check circuit that is running at the same time.
(0 or more errors) - It can be determined that the entire frame has been corrupted by some kind of noise in this frame. Even if the data of the second RAM (B126) is sent to the correction circuit as it is, it is clear that the correction will be insufficient in terms of the correction capability.Therefore, the RAM select circuit 23
The RAM changeover switches 28 and 29 are controlled via the RAM changeover switches 28 and 29 to stop switching. Then, the 16th
As shown in the time chart in the figure, the output data can be configured such that the contents of the first RAM (A125) of the previous frame are output, and the contents of the second RAM (I126), which have many errors, are not output.

FIG. 17 shows a case where this embodiment is performed using another correction method. As mentioned earlier, in this helical scan method, data is input intermittently.

This real m-column utilizes this, and as shown in FIG. 17, the correction circuit is operated during the time from the end of data input and writing to the RAM until the next write, and the data to be corrected is uses a method that rewrites the data in the RAM at that point. Also, while data is being written and corrected in this RAM, data is output from the other RAM (which holds the data of the previous frame) at regular intervals (RAM read state ).

On the other hand, at time 32 in the time chart (Figure 17), when the data in the second RAM (B126) is corrected, if there is error data that exceeds the correction capacity and a large amount of uncorrectable data occurs, the following RAM switching is stopped in each frame.Then, the same content as the previous frame is outputted as the output data, and noise due to erroneously corrected data or erroneous data can be prevented from being output.

*8U video PCM using rotary head
It is clear that the circuit of this embodiment can also be applied to audio.

(Effects) As described above, according to the present invention, when the frame pattern that is the synchronization signal is not detected and the synchronization signal is not supplemented at the correct position, or when the number of data errors in the frame is extremely When the amount increases, R corresponding to reading the output data
Since AM is maintained as the RAM of the previous frame and data is output from the RAM, noise (sound noise) in the output signal can be prevented.

Furthermore, by expanding one frame data over two or more frames and outputting it, it is possible to output data that is close to correct data.

[Brief explanation of drawings]

FIG. 1 is a schematic diagram of the data format within a frame, FIG. 2 is a diagram showing a bit interleaving matrix, FIG. 3 is a block diagram of the first embodiment of the present invention, and FIG. 4 is a diagram of the third embodiment of the present invention.
Figure 5 is an output data waveform diagram of the RA of the first embodiment.
FIG. 6 is a time chart showing another example of the operation of the RAM of the first embodiment. FIG. 7 is a block diagram of the second embodiment of the present invention. FIG. 8 is a time chart explaining an example of the operation of the RAM of the second embodiment, FIG. 9 is a time chart showing another example of the operation of the RAM of the second embodiment, and FIG. A block diagram of the third implementation, FIG. 11 is a diagram showing the relationship between the head and tape of a helical scan type PGM tape deck, FIG. 12 is a schematic structural diagram of the PGM tape deck, and FIG. 13 is a signal recorded on the tape. 14 is a block diagram of the fourth embodiment of the present invention, FIG. 15 is a circuit diagram showing a specific example of the RAM select circuit and RAM changeover switch of FIG. 14, and FIG. 16 is a block diagram of the fourth embodiment of the present invention. A time chart showing an example of the circuit operation of the fourth embodiment, and FIG. 17 is a time chart showing another example of the operation of the RAM of the fourth embodiment. 6... Synchronous signal detection circuit, 7... Descrambling circuit, 8... RAM writing circuit, 9... Correction circuit, 10... Switch, 11, 12.14... R
AM, 15...Switching circuit, 21...CRC check circuit, 23...RAM select circuit・25.2
6...RA, M, 27...Correction circuit, 13゜30...Data output circuit Patent attorney Michihito Hiraki Fig. 11 Fig. 12

Claims (1)

[Scope of Claims] (1) A signal sequence in which a signal obtained by pulse modulating an information signal such as voice is divided into frames on the time axis, and an error detection code or correction code is added to the information signal completed within the frame. , means for detecting a frame pattern (synchronization signal) indicating the beginning of an l frame in a PCM reproducing device for transmitting or reproducing the original information signal via a recording medium;
At least two frame data storage means, means for switching between the frame data storage means so that when one of the frame data storage means is being written, the other is read out, and error detection and correction of the read data. and at least one action occurs when the frame pattern detection means detects no frame pattern and the data error detection and correction means detects that the data cannot be corrected. 2. A PCM reproducing apparatus according to claim 1, wherein said PCM reproducing apparatus stops switching said storage means and replaces intra-frame reproducing data with previous frame reproducing data. (2) When the frame pattern detection means does not detect a frame pattern, or when the data error detection and correction means detects that the data cannot be corrected, expand the reproduced data within the frame into multiple frames; A patented PCM reproducing device characterized by being adapted to regenerate. {3} A signal obtained by pulse-modulating an information signal such as voice is divided into frames on the time axis, and a signal sequence in which an error detection code or correction code is added to the information signal completed within the frame is transmitted or recorded. In a PCM reproducing device that reproduces the original information signal via a medium, means for detecting a frame pattern (synchronization signal) indicating the beginning of one frame, means for detecting errors in input data, and at least two frames. the frame data storage means, means for switching the 6C storage means so that when one of the frame data storage means is being written, the frame data storage means is read from the other; and means for correcting the read data; When a large amount of errors 9 that cannot be corrected are detected by the means for detecting errors υ in input data, switching of the means for switching the storage means is stopped, and intra-frame playback data is replaced with previous frame playback data. A PC characterized by
M playback device. (4) The means for detecting errors in the input data is a CRC
Patent characterized by being a check circuit