JPS60558A - Data transfer controlling system - Google Patents

Abstract

PURPOSE:To speed up DMA by making bus occupation exclusion control by a lower unit itself when the lower unit makes DMA through a common bus in interlace mode. CONSTITUTION:Prior controlling mechanism for lower units-1,-2 is not provided in a C-BUS controlling device 12. Instead of it, the lower unit-1 generates a transfer permission signal TA to the lower unit-2 when the unit-1 itself has no data transfer request. When the unit-1 has data transfer request to the lower unit-2, and received the transfer permission signal TA, outputs a C-BUS occupation request signal REQ, and when the transfer permission signal TA becomes off, completes data transfer in specified time.

Description

DETAILED DESCRIPTION OF THE INVENTION Technical Field of the Invention The present invention relates to
This relates to an MA data transfer control method.

Prior Art and Problems Lower-level devices perform DMA (D
When performing direct memory access, it is necessary to control the occupancy of a common bus, but conventionally, a priority control mechanism has been provided for the common bus, and collective control has been performed using this. To explain this with reference to Figures 1 and 2, in these figures, 10 is a common bus (C-BUS), 12 is its control unit (CPU), and 14.16 is a lower device, and these are as shown in the figure. connected to.

The lower-order devices 14 and 16 are line adapters, disk adapters, etc., and although a large number may be provided depending on the case, only two are shown in the figure. Figure 1 is called the parallel priority control type, in which when performing DMA in incremental mode, each lower device raises the request signal REQ for each transfer, and performs priority processing by the C-BUS priority control mechanism. In addition, the control device 12 sends an authorization response signal GACK if the request is accepted.
, which causes the lower device to enter DMA.

There is no communication between lower-level devices, and if there is a DMA request, RE is sent.
If Q is raised and ACK is returned, DMA is entered and negative response NAC
If K is returned, wait. This is called a priority control type, in which the request signal REQ passes through each lower-level device from the lowest lower-level device to the upper lower-level device, and then to the control device 12, and the permission response signal ACK is sent in the opposite direction. The lower-level device that made the request picks it up and enters the DMA.

Since the signal ACK is entered in the order of the closest to the control device 12, if a plurality of lower-order devices raise REQ and ACK is returned, the lower-order device closest to the control device 12 will take it in. In other words, the order of priority is the one closest to the control device (as viewed from the ACK signal line), and the farthest lower-order devices come later.

By the way, with the advancement of technology, the data transfer speed of magnetic disk devices has become faster, and C-BUS designed using conventional technology has become faster.
The speed limit of the DMA circuit is approaching. In addition, serial data transfers that require high-speed data transfer, such as optical loops, have been put into practical use one after another, and high-speed D
It became necessary to perform MA. To deal with this, a high-speed C-Bus may be provided, but all the control units connected to the C-Bus will need to be changed, which naturally increases costs.

OBJECTS OF THE INVENTION The present invention seeks to provide a data transfer control method that allows connection of state-of-the-art disk devices, optical loop interfaces, etc. to data processing systems having slow DMA control mechanisms.

If high-speed DMA is operated in parallel in a system where DMA transfer control is slow, there will be a large time loss due to C-BUS switching, leading to a decrease in efficiency. Furthermore, due to the nature of the serial loop interface, it is impossible to perform exclusive operation control using software. To address these problems, the present invention attempts to provide a transfer control system that enables DMA for high-speed disks, optical loops, etc., specifically, a C-B'US exclusive control system.

Composition of the Invention The present invention is a data transfer control method for a system in which a central processing unit and a plurality of lower-order devices are connected to a common bus, and the common bus is occupied in incremental mode when the lower-order devices transfer data. Lower-level device A generates a transfer permission signal when there is no transfer request, and lower-level device B with a lower priority level performs direct memory access when there is a transfer request and the transfer permission signal is issued. turns off the transfer permission signal when a transfer request occurs, and as a result, lower-order device A stops direct memory access within a predetermined time, and lower-order device A discontinues direct memory access after a certain period of time after turning off the transfer permission signal, or lower-order device B The present invention is characterized in that direct memory access is started at the point when the in-transfer signal generated during direct memory access is turned off, and this will be described in detail below with reference to embodiments.

Embodiment of the Invention FIG. 3 shows an example of a system for carrying out the present invention.
The same parts as in the figure and FIG. 2 are designated by the same reference numerals.

20 is an optical loop, 22 is a magnetic disk device, 14
．． 16, that is, lower unit 1 and number 2 are adapters for these optical loops and disks.

There may be many lower-level devices, but only two of them are shown here. In the present invention, (-BUS4 lower device-1,
A priority control mechanism for the same 2 is not provided.Instead of 1°, the lower device 1 and the same 2 are set as follows.

That is, when the lower device 1 does not have a data transfer request, it generates a transfer permission signal TA to the lower device 2. Furthermore, when the lower device-2 has a data transfer request and receives the transfer permission signal TA, it outputs the C-BUS occupancy request signal REQ, and when the transfer permission signal TA turns off, it outputs the C-BUS occupancy request signal REQ within a predetermined time. In other words, the data transfer ends (no REQ is issued) at a point where the DMA is still in progress (or at a break point). Also, the lower device-1 has a certain amount of data
- It is possible to wait until the lower device-2 completes data transfer (for a predetermined period of time).

To explain the operation with reference to the time chart in Fig. 4, lower-level device-1 issues transfer permission to another lower-level device-2 when there is no transfer request to itself, and lower-level device-2 transfers data to itself. If there is a request and the lower device-1 has issued transfer permission, a C-BUS occupancy request redemption code REQ is generated and the C-BUS
- Start a DMA operation using the BUS, and
During the transfer, the signal T indicating that the transfer is in progress is raised. , when a transfer request occurs to the lower device-1, the lower device-1 issues a transfer permission signal TA.
When lower device-2 detects this, it stops the -BUS DMA operation and turns off transfer request transmitting signal T. Lower device-1 detects this and turns off C - BUS DMA operation begins. When the DMA is completed, the lower device-1 raises the transfer permission TA again, and in response, the lower device-2 raises the transmitting signal T if there is a new transfer request.
is issued and resumes C-BUS DMA operation. During this time C
-The right to use the Bus remains held by the lower devices -1 and -2.

Such control enables exclusive control of DMA operations between lower-level devices, giving priority to lower-level device-1.

According to this method, it is possible to connect peripheral devices incorporating the latest technology without changing the current device itself, and it is possible to make simultaneous operations appear to software, making control easier.

FIG. 5 shows a modified example. In this case, when a transfer request occurs to lower-level device-1, transfer permission is turned off, and lower-level device-2
is the same as Figure 4 in that it stops DMA at a certain interval even during DMA, but in Figure 5 lower device-2
Since the transmitting signal T is not raised during M'A, the lower-level device-1 has no means of knowing that the DMA of the lower-level device-2 has ended. Therefore, after turning off the transfer permission, the lower-level device-1 starts a timer to monitor the time, and when a predetermined period of time has elapsed, the lower-level device-2 assumes that the DMA has been completed or interrupted and starts its own DMA. When this DMA is completed, transfer permission is issued again, and the lower device-2 then resumes DMA if there are still transfer requests.

Since this method is a time monitoring type, the lower device-2 is DMA
There are some drawbacks, such as lower-level device-1 cannot enter DMA unless it waits for a certain period of time, even when lower-level device-2 is not in use.
has the advantage of not having to generate a signal during transmission.

FIG. 6 is a diagram showing the operation of the conventional method. If there is a transfer request in both lower-level device-1 and lower-level device-2, REQ is raised, and since lower-level device-1 has a higher priority than lower-level device-2, the lower-level device Even if -2 is in DMA, if there is a transfer request, it enters DMA and the DMA of lower device -2 is stopped. DMA is performed for each predetermined block, and at the end of each block, the DMA is transferred to the DMA of a lower-level device with a lower priority level.
2, when the DMA of the lower device 1 starts, C-BUS switching cycles occur frequently, and the ratio of data transfer using the C-Bus actually decreases, resulting in poor bus efficiency.

As described in detail, according to the present invention, bus exclusive control is performed by the lower device itself, there is no need to provide a control mechanism for this control on the common bus, and C-BUS REQ is performed every time a transfer request occurs. , ACK exchanges are not required, and the lower device can immediately enter DMA after confirming that the conditions are met. In this way, according to the present invention, a peripheral device incorporating the latest technology can be used without changing the current device itself.
This provides advantages such as connection can be made without much deterioration of BUS efficiency, and simultaneous operations can be made to appear to software, making control easier.

[Brief explanation of the drawing]

1 and 2 are block diagrams explaining a conventional transmission control system, FIG. 3 is a block diagram showing an embodiment of the present invention, and FIGS. 4 to 6 are time charts for explaining the operation. In the drawing, 10 is a common bus, 12 is a central processing unit, 14.
16 is a lower device, TA is a transfer permission signal, and T is a transmitting signal. Applicant Fujitsu Limited Representative Patent Attorney Minoru Aoyagi

Claims (1)

[Claims] In a data transfer control method in a system in which a central processing unit and a plurality of lower-order devices are connected to a common bus, and the group to which the lower-order devices transfer data occupies the common bus in an incremental mode, the priority level is high. Lower device A generates a transfer permission signal when there is no transfer request of its own, lower device B with a lower priority level performs direct memory access when there is a transfer request of its own and the transfer permission signal is issued, The lower device A turns off the transfer permission signal when a transfer request occurs, causing the lower device B to stop direct memory access within a predetermined time, and the lower device A turns off the transfer permission signal after a certain period of time. Alternatively, a data transfer control method is characterized in that the direct memory access is started at the time when the lower device B turns off the transfer raw signal generated during the direct memory access.