JPS6059657U - Sampling clock creation circuit - Google Patents
Sampling clock creation circuitInfo
- Publication number
- JPS6059657U JPS6059657U JP15230183U JP15230183U JPS6059657U JP S6059657 U JPS6059657 U JP S6059657U JP 15230183 U JP15230183 U JP 15230183U JP 15230183 U JP15230183 U JP 15230183U JP S6059657 U JPS6059657 U JP S6059657U
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- sampling clock
- digital signal
- output
- signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Synchronisation In Digital Transmission Systems (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Abstract] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図はテレビ文字多重信号の構成を示す図、第２図は
従来のサンプリングクロック作成回路を示すブロック図
、第３図は本考案のサンプリングクロック作成回路の一
実施例を示すブロック図、第４図はその実施例に使用す
る可変遅延回路の一具体例を示す回路図である。
１５：位相ロックループ。
７ ゛FIG. 1 is a diagram showing the configuration of a television character multiplex signal, FIG. 2 is a block diagram showing a conventional sampling clock generation circuit, and FIG. 3 is a block diagram showing an embodiment of the sampling clock generation circuit of the present invention. FIG. 4 is a circuit diagram showing a specific example of a variable delay circuit used in this embodiment. 15: Phase-locked loop. 7゛
Claims (2)
該クロック信号に同期したデータがこの順に挿入されて
伝送される型式のデジタル信号を受信して、上記データ
の抜取りのためのサンプリングクロックを作成するため
の回路であって、前記デジタル信号が入力される可変遅
延回路と、この遅延回路め出力に応答して発振するリン
ギング発振回路と、この発振回路の出力信号を比較入力
とし前記デジタル信号を基準入力として前記可変遅延回
路を制御する位相ロックループと、前記リンギング発振
回路の出力をサンプリングクロックとして取り出す回路
接続とを備えてなるサンプリングクロック作成回路。(1) Receive a digital signal of the type in which a reference clock signal and data synchronized with the clock signal are inserted in this order into each data packet for transmission, and create a sampling clock for sampling the data. The circuit includes a variable delay circuit to which the digital signal is input, a ringing oscillation circuit that oscillates in response to the output of the delay circuit, and an output signal of the oscillation circuit as a comparison input and the digital signal as a reference. A sampling clock generation circuit comprising, as an input, a phase-locked loop for controlling the variable delay circuit, and a circuit connection for taking out the output of the ringing oscillation circuit as a sampling clock.
接続によって構成され、その各段のＩ２Ｌ素子のインジ
ェクション電流が前記位相ロックループで制御されるこ
とにより、遅延時間が制御されるものであることを特徴
とする請求 囲第１項記載のサンプリングクロック作成回路。(2) The variable delay circuit is configured by a multi-stage cascade connection of I2L elements, and the delay time is controlled by controlling the injection current of the I2L element in each stage by the phase-locked loop. The sampling clock generation circuit according to claim 1, characterized in that:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15230183U JPS6059657U (en) | 1983-09-30 | 1983-09-30 | Sampling clock creation circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15230183U JPS6059657U (en) | 1983-09-30 | 1983-09-30 | Sampling clock creation circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6059657U true JPS6059657U (en) | 1985-04-25 |
| JPH0218613Y2 JPH0218613Y2 (en) | 1990-05-24 |
Family
ID=30337258
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP15230183U Granted JPS6059657U (en) | 1983-09-30 | 1983-09-30 | Sampling clock creation circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6059657U (en) |
-
1983
- 1983-09-30 JP JP15230183U patent/JPS6059657U/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0218613Y2 (en) | 1990-05-24 |
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