JPS6059871A - Frame signal synchronizing system - Google Patents

Abstract

PURPOSE:To prevent the erroneous detection of a frame signal at an erroneous position by forecasting the frame signal position of an individual signal line from the frame signal position of a common signal line in a small scale station in a satellite communication system. CONSTITUTION:The clock frequencies of the common signal line and the individual signal line are synchronized at a base station and the timewise relative position of a periodic frame signal inserted to each line is made constant and the result is transmitted. Each small scale station forecasts the time position of the frame signal of the individual signal line from a frame signal synchronizing pulse obtained from the frame signal detection circuit 51 of the common signal line. Since only the frame signal at the forecast time position is detected, the detection of the frame signal of the individual signal line at an erroneous position is prevented.

Description

DETAILED DESCRIPTION OF THE INVENTION (Technical Field) The present invention relates to means for detecting frame signals from received line information in satellite communications.

(Background Art) In a communication system consisting of a base station and a large number of small stations, each small station constantly receives information about a common signal line from the base station, and is unable to transmit call signals between it and the base station. A demand-assign 5CPC system is known in which an individual signal line (call signal line) is set up only when necessary. In such a system, conventionally the clock frequency of the individual signal line and the time position of the frame signal were set independently of those of the common signal line. For this reason, as will be explained below, if a frame signal of an individual signal line is erroneously detected at the wrong position, there is a drawback that line information is lost over a large number of frames.

FIG. 1 shows the configuration of a conventional frame signal detection circuit. In FIG. 1, 1 is a demodulated signal input terminal, 2
is a reproduced clock input terminal, 3 is a gate, 4 is a frame signal detector, 5 is a shift register, 6 is a comparator, 7 is a sign of the frame signal, 8 is a frame signal judger, 9 is M consecutive non-detection Judgment device, 10, gate control pulse generator, 11
is a frame signal synchronization pulse output terminal. FIG. 2 shows the waveforms at points a and b in FIG.
The signal from j6+t, to (1o 9 III to t12 is the frame signal period. The demodulated signal of the line information input to the terminal 1 in FIG. The demodulated signal at each stage is compared with a frame signal code 7 by a comparator 6, and a frame signal determination unit 8 performs frame signal determination.

This judgment output is inputted to the continuous non-detection judgment unit 9 for M times.
It is determined whether there is synchronization/'i deviation more than once.

If the synchronization state has lost synchronization M times or less, the determiner 9 outputs a synchronization pulse to the terminal 11, and at the same time inputs the synchronization pulse to the gate control pulse generator 10 that predicts the frame signal position to determine the time position of the next frame signal code. A gate pulse is generated to open gate 3. In addition, gate 3
is controlled by the generator 10 to remain open while the determiner 9 determines that the frame signal is out of synchronization, and has no function of generating a predictive gate pulse for the position of the first frame signal. For this reason, the determiner 9 in FIG.
As shown in the waveform of FIG. 2(C) with M value of 2, if the first frame signal position is mistakenly detected, the information at the beginning of the demodulated signal will be lost. Furthermore, in order to reduce the probability of erroneously detecting a frame signal at the wrong position, it is necessary to increase the code length of the frame signal, which will result in a decrease in the information transmission efficiency of the line. Furthermore, if the M value of the determiner 9 is made small in order to reduce the amount of information that is corrupted at the beginning of the demodulated signal, a disadvantage arises in that synchronization is more likely to occur.

(Problem to be solved by the invention) In order to solve this drawback, the present invention synchronizes the clock frequencies of the common signal line and the individual signal line at the base station, and adjusts the relative temporal position of the periodic frame signal inserted into each line. The signal is transmitted from the base station as a constant, and each small station predicts the frame signal position of the individual signal line from the frame signal position of the common signal line. This prevents erroneous position detection.

Hereinafter, it will be explained in detail using the drawings.

(Structure and operation of the invention) FIG. 3 shows an embodiment of the base station side of the present invention, and FIG.
FIG. 5 is a waveform diagram for explaining the operation shown in FIG. 5, which shows an embodiment of the present invention on the small-sized station side. Figure 3 shows 2
1 is an information input terminal of the common signal line, 22-1 to 22-
N is an information input terminal for the individual signal line, 23 is a multiplexing circuit for the common signal line, 24-1 to 24-N are multiplexing circuits for the individual signal line, 5 is a clock frequency oscillator source, and 26 is a multiplier/divider. 27 is a timing generator, Numa is a common signal line frame signal generator, 29 is an individual signal line frame signal generator, 30-1 to leap-N are delay devices, 31 is a common signal line modulator, 32 -1 to 32-N are individual signal line modulators, 33 is a multiplexer, and 34 is an output terminal.

In FIG. 3, the output of the clock oscillation source A is branched into three branches: one goes to the frame signal timing generator 27, one goes to the modulator 31, and one goes through the X and A multiplier/frequency divider 26. and are supplied to modulators 32-1 to 32-N, respectively. The output of the timing generator 27 is guided to frame signal generators 28 and 29 inserted into the common signal line and the individual signal lines, and the output multiplexing circuits 23 and 24-
1 to 24-N are multiplexed with information data input from terminals 21 and 22-1 to 22-N.

The output of the common signal line circuit 23 is directly supplied to the modulator 31, but the output of the individual signal line circuits 24-1 to 24-
For example, as shown in the waveforms in FIGS. 4(a) and 4(t), the output of The modulator 32- is transmitted via delay devices 30-1 to 30-N whose delay times are adjusted in advance so that the
1 to 32-4 paid. The output of each modulator is sent to the multiplexer 33
The signals are multiplexed at the terminal 34, and a transmission signal is obtained via the terminal 34.

Figure 5 shows the configuration of the frame signal detection circuit of a small station, where /IJ is the reproduced clock input terminal of the individual signal line, /12 is the demodulated signal input terminal of the individual signal line, and 7I3
44 is a gate, 45 is a frame signal detector, 46 is a frame signal determiner, 47 is an M consecutive non-detection determiner, 48 is a frame signal synchronization pulse output terminal, and 49 is a common frame signal detection circuit for the individual signal line. 50 is a demodulated signal input terminal of the common signal line,
51 is a frame signal detection circuit for the common signal line, 52 is a frame signal synchronization pulse output terminal for the common signal line, and 53 is a gate control pulse generator. In the figure, the recovered clock and demodulated signal of the individual signal line sent out from the base station are supplied to a circuit 43 via terminals 41 and 42, respectively.

On the other hand, the demodulated signal of the common signal line and the reproduced clock sent from the base station are supplied to the circuit 51 via terminals 49 and 50, respectively. The circuit 51 has a configuration similar to that explained in FIG. 1 and outputs a frame signal synchronization pulse in the same manner, but the operation of the circuit 43 differs in that it is located below the wall. That is, the frame signal synchronization pulse obtained from the output terminal 52 of the common signal line is supplied to the gate control pulse generator 53, the gate 44 is closed, and the temporal position of the frame signal of the individual signal line is predicted, and the opening/closing of the old gate is performed. It is to control. That is, the gate 44 is closed at a time predicted from the time position of frame 1 on the common signal line, and only frame 1 on the individual signal line is applied to the frame signal detector 45 via the gate 44. The construction of frame signal detector 45 is known to those skilled in the art. As a result, only the frame signal periodically inserted into the received individual signal line passes through the gate 44, and the frame signal detector 45 of the individual signal line erroneously detects the frame signal at the wrong position. This can be prevented.

(Effects of the Invention) As explained above, the time positions of the frame signals of the individual signal line and the common signal line to be transmitted by the base station are set in a fixed relationship, and in the small station, the frame signals can be obtained from the frame signal detection circuit of the common signal line. The time position of the frame signal of the individual signal line is predicted from the frame signal synchronization pulse, and only the 7 frame signal at this predicted time position is detected, so the frame signal of the individual signal line is erroneously detected at the wrong position. There's nothing left to do. This has the advantage of preventing information from being lost at the beginning of the signal on the individual signal line.

Furthermore, conventionally, it has been necessary to set the code length of the frame signal to be long in order to reduce the probability of false detection. However, by applying the method of the present invention, there is no need to consider this probability of false detection of individual signal lines, which makes it possible to shorten the code length of frame signals and improve the information signal transmission efficiency of individual signal lines. It has the advantage of being expensive.

Furthermore, in the present invention, since the clock signals of the common signal line and the individual signal line are sent out synchronously from the base station, the clock signal regenerated by the demodulation circuit of the common signal line is used as the clock signal of the individual signal line. There are advantages that can be used.

[Brief explanation of drawings]

Fig. 1 is a diagram showing the configuration of a conventional frame signal detection circuit, Fig. 2 is a diagram showing waveforms at points a and b in Fig. 1, and Fig. 3 is a diagram showing the waveforms at points a and b in Fig. 1.
The figure shows an embodiment of the present invention on the base station side, FIG. 4 is a waveform diagram for explaining the operation of FIG. 3, and FIG. 5 shows an embodiment of the present invention on the small station side. This is a diagram. 1... Demodulated signal input terminal, 2... Regenerated clock input terminal, 3... Gate, 4... Frame signal detector,
5... Shift register, 6... Comparator, 7... Frame signal sign, 8... Frame signal determiner, 9...
M-times continuous failure determination device, 10... Gate control pulse generator, 11... Frame signal synchronization pulse output terminal, 2]
...Common signal line information input terminal, 22-1 to 22
-N... Information input terminal of individual signal line, 23... Multiplexing circuit of common signal line, 24-1 to 24-N...
Multiplexing circuit for individual signal lines, 25...Clock frequency oscillator source, 26... Multiplier/divider, 27... Timing generator, 28... Frame signal generator for common signal line, 29...・・Frame signal generator for individual signal line,
30-1 to 30-N are delay devices, 31...common signal line modulator, 32-1 to 32-N...individual signal line modulator, 33...multiplexer, 34... Output terminal, 41
...Regenerated clock input terminal of individual signal line, 42...
・Demodulated signal input terminal of individual signal line, 43... Frame signal detection circuit of individual signal line, 44... Gate, 4
5... Frame signal detector, 46... Frame signal determiner, 47... M times continuous non-detection determiner, 48...
Frame signal synchronization pulse output terminal, 49...Regenerated clock input terminal of common signal line, 50...Demodulated signal input terminal of common signal line, 51...Frame signal detection circuit of common signal line, 52... Frame signal synchronization pulse output terminal of common signal line, 53...Gate control pulse generator. Patent applicant Nippon Telegraph and Telephone Public Corporation Patent application agent Megumi Yamamoto

Claims (1)

[Claims] A communication system that configures a communication line between a base station and a number of small stations or mobile stations via satellites, with a common signal line that transmits information from the base station to each small station, and a common signal line that transmits information from the base station to each small station. Regarding multiple individual signal lines that transmit individual information to stations, the clock frequencies of the two types of signal lines, common and individual, are synchronized with each other, and a periodic frame signal and each individual signal are inserted into the common signal line. The base station transmits this line information by keeping the temporal relative position of the periodic frame signal inserted into the line constant, and each small station receives the line information of this common signal line and uses the line. A frame signal synchronization method characterized by detecting the time position of a frame signal and predicting the frame (g) position of a received individual signal line based on this result to establish the cycle of the frame signal.