JPS6059902A - Train control receiver - Google Patents

Abstract

PURPOSE:To facilitate the collation of the speed of a train and to enhance the fail-safety by constructing to apply a frequency signal multiplied by a frequency multiplier to a speed checker to check the speed. CONSTITUTION:A frequency signal of a speed command signal applied from an envelope detector 4 is converted by a frequency multiplier 8 to a frequency signal proportional to the allowable speed of a train to be meant, discriminated at a level by a level detector 10 through a variable filter 9, and outputted as the output of a receiver to a speed checker 6. Since a speed detection signal from a speed detector 7 of another input of the checker 6 is inputted as a frequency signal proportional to the speed of a train, the checker 6 eventually checks the frequency signal proportional to the allowable speed of the train from a train control receiver similarly as the frequency signal proportional to the speed of the train, thereby very facilitating the check of the speed in the checker 6. Further, the fail-safety can be enhanced.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention is suitable for use in automatic train control devices (hereinafter referred to as ATC devices), automatic train stop devices (hereinafter referred to as ATS devices), etc. Relating to a control receiver.

Prior Art As illustrated in FIG. 1, a conventional train control receiver of this type receives a speed command signal flowing to a ground track circuit etc. through an on-board antenna 1, amplifies this received signal with an amplifier 2, After noise components are removed by a filter 3, envelope detection is performed by an envelope detector 4, and the signal is input to a speed command signal identification circuit 5.

The speed command signal is usually given as a frequency signal that differs for each allowable speed. In the speed command signal identification circuit 5,
These frequency signals are individually separated and sorted using a filter or the like, and are further provided with operation and fall times to form a lower priority logic, and then are output to the speed verification section 6 as a receiver output.

The speed checking section 6 checks the output of the receiver and the speed detection signal inputted from the speed detecting section 7, and controls the speed of the train based on the checking result.

Disadvantages of the prior art By the way, in the conventional train control receiver described above, in order to ensure fail-safeness of the system when allocating frequencies to each speed command signal, high speed command signals are assigned low frequencies, while high speed command signals are assigned low frequencies. is assigned, and there is no total heat proportionality relationship between the permissible train speed implied by the speed command signal and its frequency. Therefore, in the speed checking section 6,
In order to compare the speed command signal and the speed detection signal inputted from the speed detection section 7, the speed command signal must be converted into a frequency signal proportional to the permissible train speed that it represents. The problem was that the structure was complicated and the verification process was troublesome.

OBJECTS OF THE INVENTION It is an object of the present invention to solve the above-mentioned conventional problems and provide a train control receiver that facilitates speed checking and is highly fail-safe.

Structure of the Invention In order to achieve the above object, the present invention provides a train control receiver that detects and identifies a speed command signal received as a frequency signal, in which the speed command signal is proportional to the permissible train speed that it represents. The present invention is characterized in that it is equipped with a frequency multiplier circuit that converts the frequency into a signal of a given frequency and outputs the signal, and outputs the output of the frequency multiplier circuit as a receiver output to the speed checking section.

Embodiment FIG. 2 is a block diagram of a train control receiver according to the present invention. In the figure, the same reference numerals as in FIG. 1 indicate the same components. 8 is a frequency multiplier circuit. The frequency multiplier circuit 8 converts the frequency signal, which is the speed command signal, into
It is converted into a frequency signal proportional to the permissible train speed. In this embodiment, the frequency multiplier circuit 8 multiplies the low frequency signal after envelope detection by the envelope detector 4, which is determined by the lower priority parallel signal (a) given from the speed command signal identification circuit 5. The frequency is multiplied by . For example, the frequency signal that is the speed command signal is 16H.
When z means the current speed of 75 km/hour, the frequency multiplier circuit 8 sets the multiplication power so that a 750 Hz frequency signal proportional to the current speed of 75 km/hour, which is meant by this 16 Hz frequency signal, is output. It is determined.

An example of such a frequency multiplier circuit 8 is disclosed in Japanese Patent Application No. 57-2.
No. 3145, Japanese Patent Application No. 57-25638, Japanese Patent Application No. 1987-
Examples include those disclosed in No. 25639 or Japanese Patent Application No. 57-204859. The basic principle of the frequency multiplier circuit disclosed in these prior arts is that, as shown in FIG. The code frequency fin is converted into a code frequency signal, and this code frequency fin is applied to a random access memory (hereinafter referred to as RA) by a write control pulse CTG given from a control circuit 82.
83 (referred to as M), and then read out using a read control pulse CT2 corresponding to the data written in this RAM 83. At this time, with respect to the input code frequency fin, the period T of the write control pulse CT+ and the above Read control pulse C
The circuit has a circuit configuration that outputs a signal multiplied by the ratio of the period τ of T2, (T/τ). Therefore, the multiplication power is determined by the ratio (T/τ) of the period T of the write control pulse CT and the period τ of the read control pulse CT2, and any frequency and waveform can be faithfully multiplied by any multiplier. obtain.

When applying this frequency multiplication circuit to the present invention, the period T of the write control pulse CT and the read control pulse CT
The ratio (T/τ) of the period τ of 2 is determined by the speed command signal identification circuit 5.
The setting may be made based on the lower priority parallel signal (a) given from .

Reference numeral 9 denotes a variable filter composed of, for example, a digital filter, a switched capacitor, a filter, or the like. The variable filter 9 has a selected center frequency that is variable so as to pass the frequency signal multiplied by the frequency multiplier circuit 8 based on the lower priority parallel signal (A) given from the speed command signal identification circuit 5. Set. 10 is a level detector.

In the above circuit configuration, the frequency signal serving as the speed command signal given from the envelope detector 4 is converted by the frequency multiplier circuit 8 into a frequency signal proportional to the permissible train speed, which is passed through the variable filter 9. Level detector 1
The level is determined at 0 and outputted to the speed check section 6 as a receiver output. Here, the speed detection signal from the speed detection section 7, which is another input to the speed checking section 6, is input as a frequency signal proportional to the train speed, so the speed checking section 6
In the end, the frequency signal proportional to the train permissible speed from the train control receiver is compared with the frequency signal also proportional to the train speed, which greatly facilitates speed checking in the speed checking section 6.

Further, since the configuration is such that the frequency signal multiplied by the frequency multiplier circuit 8 is given to the speed check section 7 to perform speed check, the frequency multiplier circuit 8 and its preceding circuit or the speed command signal identification circuit 5, the frequency multiplier circuit 8 If a failure or the like occurs in the circuit section in the preceding stage, the frequency multiplied signal that is the basis for speed checking is lost, so a highly fail-safe train control receiver can be obtained.

Furthermore, in this embodiment, a variable filter 9 is provided after the frequency multiplier circuit 8, and only the frequency signal multiplied by the frequency multiplier circuit 8 is allowed to pass. There is also an advantage that the problem of superimposed waves at the blockage boundary can be solved by extracting only the speed command frequency signal of the blockage section on the lower side of either one.

FIG. 4 is a block diagram of another embodiment of the train control receiver according to the present invention. In this embodiment, a wheel diameter correction setting circuit 11 is provided, and by giving a wheel diameter correction signal (b) from the wheel diameter correction setting circuit 11 to the frequency multiplier circuit 8, the degree of multiplication in the frequency multiplier circuit 8 can be adjusted. It is determined based on the lower priority parallel signal (a) and the wheel diameter correction signal (b) from the speed command signal identification circuit.

Table 1 specifically shows the relationship between the speed command signal frequency, the corresponding displayed speed, wheel diameter correction, allowable speed after wheel diameter correction, output frequency, and multiplication degree. To explain a little more about how to read Table 1, for example, when the speed command signal frequency is 19Hz, the displayed speed is 55Km/h, and the wheel diameter correction is -1Km/h, the permissible value after wheel diameter correction is The speed is the current speed of 55Km and wheel diameter correction - IKm
The sum is 54km/h. The frequency multiplier circuit 8 converts the speed command signal frequency of 19 Hz into a signal with a frequency of 540 Hz proportional to the permissible train speed of 54 Km/h, and outputs the signal. Therefore, the frequency multiplication degree in this case is 28
．． It becomes 421. Other speed command signal frequency 16Hz, 2
The same applies to 8Hz and 35Hz.

In addition, in the case of 42) 1z, the displayed speed is OK m / h
It is. In this case, the output of the speed detector is generally not OHz, that is, direct current, but is turned off or set only at a frequency corresponding to, for example, 5 km/h.

Therefore, this amount is taken into consideration in the wheel diameter correction and is used as the receiver output. (Leaving space below) Table 1 shows summer 1. It is characterized by comprising a frequency multiplication circuit that converts the signal into a signal with a frequency proportional to the permissible train speed and outputs the signal, and the output of the frequency multiplication circuit is outputted from the train control receiver. , easy to check speed,
A highly fail-safe train control receiver can be provided.

[Brief explanation of the drawing]

Fig. 1 is a block diagram of a conventional train control receiver, Fig. 2 is a block diagram of a train control receiver according to the present invention, Fig. 3 is a block diagram of a frequency multiplication circuit, and Fig. 4 is a block diagram of a train control receiver according to the present invention. FIG. 3 is a block diagram of another embodiment of a control receiver. However, the speed check section and speed detection section are also shown. 5φ...Speed command signal identification circuit 6-fist/speed reference section 7...Speed detection section 8/e reference frequency multiplication circuit

Claims (2)

[Claims] (1) A train control receiver that detects and identifies a speed command signal received as a frequency signal includes a frequency multiplier circuit that converts the speed command signal into a frequency signal proportional to the permissible train speed that it represents. A train control receiver comprising: an output from the frequency multiplication circuit as an output to a speed checking section that checks a speed command signal and a train speed detection signal. (2) The train control according to claim 1, wherein the wave number multiplier circuit converts the frequency signal into a frequency signal proportional to the permissible train speed by taking into account the wheel diameter correction signal of the train. receiver.