JPS60683B2 - Sequence control device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a general-purpose sequence control device.

As a sequence control device that controls a controlled system such as a machine tool to operate in a predetermined process order, it is equipped with a program storage section in which the necessary control contents can be written, and is designed to standardize design and manufacturing. 2. Description of the Related Art There is a recent trend toward diversification of general-purpose sequence control devices that can easily handle changes in the specifications of a control body, changes in process order, and the like.

Programming for this type of device is performed, for example, by operating a setting key provided on a console to write a required program into a program storage section. However, in the conventional device, it is necessary to design a relay circuit to use as a basis for program settings when performing such programming. In other words, a program was obtained by first designing a circuit using relays with assisted points or non-contact points, and converting the circuit diagram into symbol keys, pool algebras, and codes. Therefore, although the design and manufacture of general-purpose sequence control devices themselves can be standardized, creating programs specific to controlled systems requires the use of relay circuits, just as in the design of conventional sequence control devices that use relays as main components. Design work is required,
There is a problem in that the advantages of standardization are diminished.
In addition, when a consumer rewrites a program to change the operating sequence or specifications of a controlled object, a relay circuit must be designed in the same way, and there is a problem that the versatility of the device cannot be fully enjoyed. Ta. Furthermore, since the capacity of the program cannot be calculated until after the design of the relay circuit is completed, there is a problem in that there is also a delay in determining the specifications of the sequence control device. The present invention has been made in view of the above circumstances, and it is an object of the present invention to provide a general-purpose sequence control device that solves the above-mentioned problems by having a configuration that allows programming according to the operation of the controlled object. do.

First, the principle of the present invention will be explained below.

Generally, one step process in sequential control (hereinafter referred to as a unit process) gives an output signal OUT to the controlled object to be controlled in the unit process n, that is, the motor, solenoid valve, etc. that constitute the controlled system, as shown in Figure 1. Then, an input signal IN responsive to the output signal OUT, that is, a signal from an operation switch, a limit switch, a timer, etc., is obtained,
Based on the result of this calculation, the center step is taken from the unit process n to the next unit process m. The present invention has been made by focusing on the fact that sequential control is configured by a combination of such unit processes.

That is, the sequence control device according to the present invention includes a process flag storage unit configured with process flag storage means (a plurality) having a function of storing the state of the unit process corresponding to the unit process being executed. , Check the set/reset state of the flag corresponding to the contents of the process flag address in the program extracted from the program storage unit in a time-sharing manner, and if the flag is in the set state, set the unit corresponding to the flag. The process (single or plural) is controlled, and at the end of each unit process, the contents for instructing the next unit process are programmed, so that the transition to the desired unit process can be performed freely. The transition between unit processes will be explained below in various cases.

The above-mentioned FIG. 1 shows the sequential transition of unit processes. In contrast, FIG. 2 shows a jump from unit process n to unit process m. In other words, content k that instructs the next unit process is programmed at the end of unit process n, and when the transition condition written in unit process n is met, the corresponding flag is set in k in the process flag storage section, and as a result, the unit Process k
The program will be executed. As shown in the figure, k=
If m (m>n+1) is programmed, the process jumps to the unit process m, and if k=n+1 is programmed, the process advances to the unit process n11. Then, the flag corresponding to n in the process flag storage section is reset, and the control execution of unit process n is completed. 3 to 5 show variations of the above-described transition.

That is, FIG. 3 shows the case where k=m (m<n), and the unit process n
Jump to the previous unit process m. FIG. 4 shows a case where a jump is made from unit process n to unit process m (m>n+1), and then step is made to unit process m+1 to separate unit processes n+1 to m-1. Figure 5 shows a transition from unit process n to unit process m (m>n+1), and then unit process m
. . m+Q are sequentially executed, then the unit process k'=n+1 is programmed at the end of the unit process m+Q, and the process returns to the unit process n11.

This is the unit process m between unit process n and unit process n11.
It means to insert ~m+Q. In exactly the same way as such a jump transition, branch control or parallel control, the opposite integrated control, and further judgment control are performed.

FIG. 10 is a process diagram when performing branch control or parallel control.

Two contents, n11 and m, are programmed as content k that instructs the next unit process at the end of unit process n.
In such a case, if the transition condition for unit process n is satisfied, unit processes n+1 and m in the process flag storage section will be
The flags assigned to each of them are set simultaneously, and unit processes n+1 and m are controlled in parallel (by time-sharing control). In other words, branch control is performed from unit process n to unit processes n+1 and m. As in the case described above, the flag assigned to unit process n is reset at the same time as the flags n+1 and m are set. FIG. 11 shows a process for integrating the control branched as described above, in which n+1 is programmed as the next unit process k of unit processes n and m.

Therefore, when the respective transition conditions are satisfied in unit processes n and m, the corresponding flags are set, and the flag corresponding to unit process n+1 is also set. The process moves to unit process n11. The above branching or merging is basically the same as the jump described above, but the decision control shown below is slightly different in content.

That is, as shown in FIG. 9, transition condition A in unit process n
The process moves to unit process n+1 or m depending on whether the expression is satisfied or not. Specifically, during the program of unit process n, unit process n
A condition for going to +1 and a condition for going to unit process m are programmed, and a transition is made to the unit process with the condition that is satisfied first of both conditions. For example, if transition condition A is satisfied (or the transition condition to unit process n11 is satisfied), that flag is set, the flag of unit process n is reset, and as a result, the transition from unit n to unit process n+1 is performed, and control of unit process m is not executed. In this way, in the apparatus of the present invention, unit processes are made to walk, perform jumps including separation and insertion, branch, integrate,
Furthermore, unit processes can be combined so that selection of unit processes is performed based on judgment.

On the other hand, when looking at the movement of the controlled object, this movement can be expressed as a combination of the above-mentioned unit processes, and this is why the device of the present invention can be easily programmed by focusing only on the movement of the controlled object. . In the programming process performed in this manner, there is no need to imagine a relay circuit that can realize the operation of each unit process. Next, the present invention will be specifically explained based on drawings showing embodiments thereof.

FIG. 6 is a block diagram showing one embodiment of the device of the present invention. A program counter 12 counts the clock signal output from the oscillator 11.

Reference numeral 13 denotes a read-only memory type program storage section, which receives the counted contents of the program counter 12 as an address selection signal and can sequentially display the contents of the address corresponding to the address selection signal from the zero address to the maximum address. There is.

FIG. 7 shows the format of one word of the program stored in the program storage section 13, which is composed of a process flag address section PFA, an instruction section ORD, and an address section ADR.
The contents of this process flag address section PFA are input to the process flag reading section 14. Reference numeral 17 denotes a process flag storage unit having a plurality of flags and having a function of storing unit processes that are being executed.

That is, the unit process being executed is stored by setting each of the flags assigned to each of the unit processes. When the process flag storage unit 17 stores a flag corresponding to the content of the process flag address field PFA read from the program storage unit 13, the process flag extraction unit 14 detects that the program related to the unit process currently being executed is If read, a predetermined signal is sent to the control section 18 and calculation section 19. Further, the contents of the instruction section ORD are input to the instruction decoder 15 and decoded, and the decoded instructions are transferred to the control section 18.
When receiving the signal from the process flag reading section 14, 8 executes the instruction by referring to the data in the address part ADR or the data in the process flag address part PFA. Table 1 lists the commands used in this device and their functions. If the command that has been decoded and transferred is an output command OUT, the control unit 18 in Table 1 sends the calculation result of the calculation unit 19 to the specified address (corresponding to the controlled device) by sending it to the input/output unit 2.
Controls 0.

If the command is an input command IN, the input at the specified address is input to the calculation unit 19. If the instruction is a logical operation instruction, an operation is performed between the input at the specified address or the process flag exported from the program storage unit 13 to the process flag logic output unit 14 and the contents of the operation unit 19, and the result is calculated. 19.

The calculation section 19 performs such calculations and storage.
If the command is a process rewriting command, data for rewriting the flag in the process flag storage unit 17 is sent to the process flag storage unit 16 according to the contents of the address field ADR. The process flag rewriting unit 16 rewrites the flag in the process flag storage unit 17 to an address read from the program storage unit, and the output unit 20 rewrites the flag in the process flag storage unit 17 to an address specified by the program from among a plurality of input/output signals. The input or output is selected, the output result is latched, and the input result is taken in.

The basic commands used in the program of the apparatus of the present invention configured as described above are shown in Table 1, but a unit process usually consists of several to several tens of command words in Table 1. configured using FIG. 8 shows an example of a program used in the apparatus of the present invention.

First, the STARTSTEP command shown in unit process 0 is normally written at the beginning of the program, and gives a command to the process flag rewriting unit 16 to set the process flag in the process flag storage unit 17 corresponding to the contents of the address field ADR. In the program example shown in FIG. 8, the process flags at addresses 1, b, and c are set to store that these unit processes 1, b, and c are currently in operation. In this example program, unit processes 1, b, and c are executed from the beginning.
This means that these three systems are controlled in parallel. As a result of this STARTSTEP command, unit processes 1, b, and c are executed in parallel by time-sharing control, and program addresses 3 to 3 are executed in parallel.
The part at process flag address 1 of 7 corresponds to unit process 1, and the part at program addresses v and v+1 corresponds to unit process c.

Unit process b is not shown in FIG. Unit processes 1, b, and c are controlled in parallel by time division control.

The first OUT command in process flag address 1 gives a command to output to address d to input/output unit 2. IN command is input e
The input/output unit 2 sends a command to select and input it to the calculation unit 19.
0 and is given to the arithmetic unit 19.

The AND instruction selects the input f, causes it to be loaded into the arithmetic unit 19, and gives a command to the input/output unit 20 and the arithmetic unit 19 to perform an AND operation with the input e read as described above.

Note that the calculation unit 19 stores the calculation result. The OR command selects the input g, reads it into the input/output unit 20, and sends a command to the input/output unit 20 and the calculation unit to cause the calculation unit 19 to perform a logical OR operation with the calculation result obtained by the AND command that has already been stored. 19, and the result of this calculation is similarly stored in the calculation unit 19.

The STEP command issues a command to the process flag rewriting unit 16 when the transition condition is satisfied as a result of the calculation of the arithmetic command in the unit process, rewrites the flag according to the contents of the address part, and causes the process to proceed to the rewritten unit process.

That is, in unit process 1 of the program shown in FIG. 8, if the transition condition is satisfied as a result of the logical operation of inputs e, f, and g, the process moves to unit process m. In the program example for unit process 1 above, logical operation instructions include AND, OR, etc.
Although an instruction in which the input at a specified address is used as an operation object has been used, the unit process a shown at program addresses z-z13 includes instructions that use process flags such as ANDSTEP and ORSTEP as an operation object. That is, in this unit process a, an AND operation is performed between the input j and the process flag c+d. If this logical product is established, the STEP command causes the step to proceed to the unit process a+1. Next, unit process c+1 at program addresses v+2 to v14
To explain the command R STEP, this command gives a command to the process flag rewriting unit 16 to forcibly reset the process flag specified by the program.

In the case of the illustrated program example, when an ERG (emergency stop signal) is input to the input/output unit 20 in unit process c, the process moves to process c11, where process flags p, q, and r are reset and this Control of unit processes p, q, and r is stopped. In other words, by writing the STARTSTEP instruction at program address 2, unit process c is constantly monitoring input ERG as a branch sequence. Other negation instructions not shown in the program example are AND NOT, ORNOT, A, as shown in Table 1.
It is used as a composite instruction with other logic operation instructions such as NDNOTSTEP and ORNOTSTEP, and performs a predetermined operation by converting input and process flag signals into negative logic signals.

In addition, the N STEP command has transition condition A as shown in Figure 9.
It is used to instruct the unit process to be transferred when the is not satisfied.

In other words, in the case of Fig. 9, N ST is applied to the last part of unit process n.
A program of EP m STEP n+1 is prepared.

In this way, the sequence control device according to the present invention advances the unit process step by step, performs jumps including separation and insertion, branches, integrates, and further selects the unit process based on judgment. By simply knowing the operation of each controlled object that makes up the controlled system, it is possible to program according to the operation, and even when there are process changes, it is possible to design relay circuits that correspond to the changes. This problem can be dealt with simply by changing the contents of the program.

Therefore, it is completely unnecessary to consider a relay circuit for realizing the operation of the controlled object when creating a program, making the work of creating a program extremely easy and quick. Furthermore, there are fewer types of program command words than those commonly used in the past, and programming itself is easy.

Furthermore, since the capacity of the program can be determined based on the operating specifications of the controlled system, there is no delay in determining the specifications of the sequence control device. As described above, the present invention has excellent effects in that it is easy to create a program for a sequence control device, and it is also possible to easily change the program when changing an operation sequence or the like.

[Brief explanation of drawings]

FIG. 1 is an explanatory diagram of the transition of a unit process in sequential control, and FIGS. 2 and 3 are process diagrams when jumping from a unit process n to the next and previous unit process m by the apparatus of the present invention, respectively.
Figure 4 is a process diagram when separating and changing a unit process using the apparatus of the present invention, Figure 5 is a process diagram when inserting and changing a unit process using the apparatus of the present invention, and Figure 6 is a main part of the apparatus of the present invention. 7 is a format diagram of a program word used in the device of the present invention, FIG. 8 is a drawing showing an example of a program used in the device of the present invention, and FIG. 9 is a diagram showing the program language used in the device of the present invention. FIG. 10 is a process diagram for performing branching control or parallel control using the device of the present invention.
Figure 1 is a process diagram for the same case where integration is performed. 11...Oscillator, 12...Program counter, 1
3...Program storage unit, 14...Process flag logic generating unit, 15...Instruction decoder, 16...
...Process flag rewriting unit, 17...Process flag storage unit 18...Control unit, 19...
- Arithmetic unit, 20... Input/output unit. Figure 1 Tsuyoshi 2 Figure Grandson 3 Figure 4 Works 5 Tsuna q Figure Festival -. Drawing brother'1 figure Tsutomu 6 figure key figure box 8 figure

Claims (1)

[Claims] 1. A process having a program storage section that stores a plurality of process flag addresses, instructions, and addresses, a program counter that cyclically reads out the contents of the program storage section, and a plurality of flags that have the function of storing a process that is currently being executed. a flag storage unit; a process flag reading unit that reads the state of a flag in the process flag storage unit corresponding to the process flag address read from the program storage unit; and a process flag reading unit that reads the flag in the process flag storage unit from the program storage unit. The process flag rewriting unit rewrites the flag to the address read from the program storage unit, and selects the input/output signal corresponding to the address read from the program storage unit from among the multiple input/output signals, and latches the output result or imports the input result. an input/output section, an instruction decoder that decodes instructions read from the program storage section, and an operation that performs a logical operation on signals input from the input/output section and the process flag reading section based on the instructions decoded by the instruction decoder. and a control unit that gives instructions to each unit according to instructions read from the program storage unit and decoded, and the control unit controls the input/output unit when the instruction is an output instruction, and also controls the input/output unit when the instruction is an output instruction. If it is a process flag rewriting command, the input/output signal or input signal from the process flag reading unit is given to the calculation unit to control it, and if it is a process rewriting command, the process flag rewriting unit is controlled to jump to an arbitrary process. A sequence control device characterized in that it is capable of simultaneously controlling a plurality of processes by having a function of storing a plurality of process flags in response to a process letter command.