JPS6070816A - Voltage comparator - Google Patents

Abstract

PURPOSE:To attain small area, low power consumption, high speed and also high accuracy by constituting a differential amplifier stage so as to perform two operating modes, preamplifier operation mode and comparator operation mode and switching the modes by a logical signal. CONSTITUTION:A voltage VDD and a voltage VSS (VDD>VSS) are applied respectively to terminals 1 and 2, and a bias voltage VB is applied to a gate of P- channel MOSFETS PMOSM1, M10 from a terminal 3. PMOSM2, M3 are input transistors and two analog comparison voltages VIN(-), VIN(+) are applied to gates 4, 5. NMOSM4, M5 are load circuits of the M2, M3 and NMOSM6-M9 are connected between the gate and drain. An input gate of a CMOS inverter comprising the PMOSM12 and NMOSM13 and a gate of the M6, M9 are connected to an input terminal 6 of a mode switching signal. On the other hand the gate of the NMOSM7, M8 is connected to an output node 7 of the inverter.

Description

[Detailed Description of the Invention] [Field of Application of the Invention] The present invention relates to a voltage comparator, and more specifically, a voltage comparator that compares the magnitude of two analog voltage levels and outputs a logic level corresponding to the result. In particular, the present invention provides a voltage comparator suitable for implementing various high-speed, high-precision A/D converters in MO8 semiconductor integrated circuits.

[Prior art]

A voltage comparator using a conventional MO8 semiconductor, for example,
EEE Journal of Sol 1d-sta
teCirCIJitSI 5C-14, A6. D.E.
C, 1979, PP965, etc.
A so-called operational amplifier type with a multi-stage cascade configuration without a phase compensation circuit was used. The multi-stage cascade configuration in this case is a natural way to achieve a large voltage gain, i.e. to compensate for the relatively low transconductance nature of the MO8 semiconductor and to ensure the desired minimum comparison voltage level. Therefore, the circuit becomes complex and large-scale.Furthermore, when high-speed operation is desired, it is necessary to increase the bias current in each stage, which increases the area occupied by the integrated circuit. Also, there was a drawback that power consumption increased.

[Purpose of the invention]

SUMMARY OF THE INVENTION An object of the present invention is to provide an MO8 semiconductor voltage comparator that eliminates the drawbacks of the conventional circuit type described above, has a small area, low power consumption, and is fast and accurate.

[Summary of the invention]

In order to achieve the above object, the present invention provides a voltage comparator in which an analog signal produced by two people is amplified by a differential amplification stage, and the output of the dJru1 corner stage is further amplified by a second amplification stage. The dynamic amplification stage includes a constant current circuit, first and second transistors whose source electrodes are commonly connected to the constant current circuit, and whose gate electrodes each have the two analogues applied thereto; The first and second load circuits are connected to the drain electrodes of the first and second transistors or the drain electrodes of the second and first transistors, respectively, according to a control logic signal.

According to the above configuration, as will be explained in detail in the following section, in the voltage comparator according to the present invention, the differential amplifier stage is in a cross-connected state with the preamplifier operating mode having a relatively small voltage gain. The configuration is such that two operation modes can be performed, and the mode switching is performed by a control logic signal, thereby eliminating drawbacks in high-speed operation and cross-connection, and providing highly accurate voltage comparison.

[Embodiments of the invention]

Hereinafter, the present invention will be explained in detail using the drawings.

FIG. 1 is a circuit diagram of an embodiment of a voltage comparator according to the present invention, and FIG. 2 is a waveform diagram for explaining the operation of the circuit.

In Figure 1, voltages VDD and VS are applied between terminals 1 and 2.
S (however, VDD-VSS>O) When force is applied, P
The gate electrodes of channel MO8) transistor (hereinafter simply referred to as PMO8) Ml and MIO are connected to VDD from terminal 3.
A bias pressure VB of -VB=C (where C is a positive constant value) is applied. Therefore, each gate-source voltage VGS of Ml and MIO is a constant voltage, so that both Ml and MIO operate as constant current devices. P
MO8, M2 and M3 are input transistors whose source electrodes are commonly connected to each other and whose transistor dimensions are equal;
Two analog specific absorption voltages, VIN and VTN, are applied to each gate electrode 4 and 5, respectively. M4 and M5 (hereinafter simply referred to as NMO8) are the load circuits for M2 and M3 above.
, M6 to M9 are connected. That is, PMO8,
M2 and NMO8, M4 drain common connection point 8, and M4
, M8 between the gate electrodes of 8 and M5, M7 between the drain common connection point 9 of M3 and M5, and the M4 gate electrode, and Similarly, M9 is connected between the gate electrodes of M9 and M5.

Furthermore, the input gate electrodes of the CMOS inverter composed of PMO8, M12 and NMOS, M13 and the gate electrodes of M6 and M9 are connected to the input terminal 6 of the mode switching signal. On the other hand, the above NMOS.

The gate electrodes of M7 and M8 are connected to the output two doors of the inverter. That is, MOS.

M6-M9. M12 and M13 are MOS load circuits
.

This is used to switch the connection between M2 and M3. Furthermore, N
M'O8 and Mll constitute an inverting amplifier using the PMO8 and MIO as constant current loads, inverting and amplifying the voltage at the first-stage differential amplification output node 9 and outputting the comparison result from the terminal 1°.

Next, the operation of each of the above components will be described.

FIG. 2 is a waveform diagram for explaining the operation of the above embodiment, in which the horizontal axis is time and the vertical axis is voltage at each part. Also, the same numbers indicate the voltage at the first same number. Now, the voltage applied to terminal 5■
The description will be made assuming that IN(g) is a constant value and the voltage VIN(g) applied to the terminal 4 is a voltage to be compared.

In the time range where time t is O≦1 (1), the operation mode switching signal at terminal 6 is at a high logic level, and therefore,
Since node 7 is at a low logic level, NMOS, M6 and M9 are on and M7 and M8 are off. Therefore, at this time, the first stage amplifier circuit (MOS) transistor (consisting of λ...11 to M5) operates as a linear differential amplifier with a relatively small voltage gain, and if VIN (T) - VIN) - VIB, then the node The voltages (VS and V,) at nodes 8 and 9 are both va "" Ve = V On, if VIN) - VIN (g) + △VIB, then VS -
■OB -△VOB, (However, the voltage waveform of node 8 is not shown in Figure 2) VS = V OB +△■O
It becomes B. Here, voltage amplification gain GA-△VOB/△VI
How much to choose B is a design issue, but usually considering the load configuration and low power consumption in this state, GA
is a relatively small value, and if ΔVIB is small, the voltage at output 10 cannot be inverted to this extent.

However, when the voltage applied to terminal 6 is changed to low logic I/bevel at t-1l, NMOS, M6 and M9 are turned off, and M7
and M8 are turned on, that is, the voltage at node 8 is N
The voltage of node 9 is applied to the gate electrode of MOS, M5, and the voltage of node 9 is applied to the gate electrode of NMOS, M4.
Loads MO8, M4 and M5 are cross-connected to each other.

Therefore, in this case, M4 is given a larger value to its gate electrode (than the potential in the preamplifier mode described above), and operates so that the ion resistance value becomes small.
The potential of the drain electrode (ie, node 8) is lower than that in the preamplifier mode described above. On the other hand, NMOS
, M5, a potential smaller than that in the preamplifier mode mentioned above is applied to its gate electrode, and the value changes to an even smaller value as mentioned above, so that the resistance value of M5 becomes smaller. increases, and the potential of its drain electrode (ie, node 9) changes to become smaller. That is, in this state, nodes 8 and 9 will be different if there is a slight difference (2△VB
O), the positive feedback operation described in 1 will rapidly increase the difference.

Therefore, as shown in FIG.
It is further amplified in the next stage inverting amplifier consisting of IO and Mll, and as a result, VIN (c) and V
The result of determining the magnitude of IN(A) can be output as a logic level that changes between the electric cooling voltage values. Moreover, since this positive feedback operation is rapid and has a large voltage gain, even if the input comparison voltage VIN(to)
Even if changes in the opposite direction, the output cannot be reversed again unless the voltage in the opposite direction is very large. In other words, once this comparison mode is applied, the result at output 10 is maintained even if the input changes during that period.

Next 1. ,=1. When the potential of terminal 6 becomes high logic level again and the mode is switched to pre-operation operation,
The voltage at node 9 (and node 8) performs an amplification operation with a small voltage gain, and therefore the potential at output node 10 is at a logic level.

Then 1=1. will return to comparison mode, but at this time,
In the example shown, the input comparison voltage (VIN) immediately before the mode switching is VIN (to) - VI11+) = -△VBj (<O)
The case is shown below. In this case, although detailed explanation will be omitted, a high logic level will be obtained at the output node 10 by the same operation as described above.

The present invention has been described in detail above, and the circuit structure of the present invention is characterized by being extremely stable against power supply voltage fluctuations during operation. That is, both the first-stage differential amplifier circuit and the next-stage inversion circuit are connected to the upper power supply VDDK.
Since MO8, Ml and MIO have a constant current source configuration, even if the power supply voltage VDD fluctuates during operation, the node 8
The voltages at nodes 1 and 9 do not fluctuate, and therefore the voltage at output node 10 is also stable. Also, if the vSS power supply side fluctuates,
Nodes 8 and 9 fluctuate at the same time by the amount of power supply voltage fluctuation, but the voltage between the gate and source electrodes of NMO8 and Mll remains constant, so the voltage at υ output node 10 is VSS.
It is stable against

As explained above, according to the present invention, a voltage comparator with a small surface, low power consumption, high speed, high stability, and high gain can be realized with an extremely simple configuration, and a high speed, high precision A/D Converters and the like can be economically integrated into a single circuit.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of an embodiment of a voltage comparator according to the present invention;
FIG. 2 is a paper pressure waveform explaining the operation of each part in FIG. 1. 1, 2.3...Power input terminal, 4,5...Analog comparison voltage input terminal, 10...Output terminal, M1 to M13...
MOS transistor.

Claims (1)

[Claims] 1. A voltage comparator configured in cascade of a differential amplification stage that amplifies the difference between two analog voltages and a second amplification stage that further amplifies the output of the amplification stage to the amplitude of the power supply voltage. In the differential amplifier stage, a first constant current circuit and first and second transistors whose source electrodes are commonly connected to the first constant current circuit and whose gates are respectively applied with the two analogues are connected. , first and second load circuits comprising transistors, and a control logic signal causes the first and second load circuits to connect to the drain electrodes of the first and second or second and first transistors, respectively. A voltage comparator comprising a switching circuit for switching connection. 2. In the voltage comparator described in item 1, the second amplification stage has a second constant current circuit, a drain electrode and a north electrode are connected in series to the second constant current circuit, and a gate electrode is connected in series to the second constant current circuit. A voltage comparator, characterized in that it is connected to the gate electrodes of the first and second transistors and has an output terminal at the drain electrode. 3. In the voltage comparator described in item 1 or 2, the first and second constant current circuits each have a third constant current circuit whose source electrode and gate electrode are connected to the first and second power sources, respectively.
and a fourth transistor, the first and second transistors
Each of the load circuits has a drain electrode connected to the drain electrodes of the first and second transistors, and a source electrode connected to the third power source. The switching circuit includes an inverter circuit that is connected between the first power source and the third power source and that receives the control logic signal as an input, and an inverter circuit that is connected between the first power source and the third power source and receives the control logic signal as an input. are connected between the gate electrodes and source electrodes of the fifth and sixth transistors, respectively; Voltage comparison with the gates of the fifth and sixth transistors as poles and seventh and eighth transistors whose drain electrodes are respectively connected to the drain electrodes of the sixth and fifth transistors. vessel. 4. 1st. In the voltage comparator according to the second or third item,
A voltage comparator characterized in that each transistor is composed of a MOS transistor.