JPS6070965A - Voltage stepup circuit - Google Patents

Abstract

PURPOSE:To accurately enhance the voltage rise by less number of circuit components by storing a charge in the capacity of the source of a depression type MOS transistor to raise the voltage. CONSTITUTION:When a clock input terminal phi is ''H'' level, drive MOS transistors of inverters I1, I2, i.e., enhancement type MOS transistors E1, E2 becomes ON, and the output terminals of the inverters E1, E2 become ground potential. When the clock input terminal phi is ''L'' level, a depression type MOS transistor D becomes OFF, the transistors E1, E2 also become OFF, and a power source voltage is outputted to the output terminal of the inverter I1. The output voltage of the inverter I1 becomes twice of the power source voltage. As a result, the transistor D2 becomes ON, and double power voltage is outputted to an output terminal Vout.

Description

Detailed Description of the Invention (Technical Field) The present invention provides a semiconductor integrated voltage circuit as a light load voltage circuit that has a simple device structure, a small number of circuit elements, high voltage increase efficiency, and can obtain a voltage boost value with high accuracy. The present invention relates to a voltage booster circuit that can be fabricated on-chip in a circuit.

(Prior art) Boosting using an enhancement type MO8) Lanzostar has been used as a compact and low power consumption boosting circuit for various electronic devices that require small size and light weight, such as electronic desktop calculators and electronic wristwatches. circuit is used. An example thereof is explained in FIG.

FIG. 1 shows a voltage doubler circuit with a CMOS configuration of enhancement type MO8) transistors. The first voltage input. The second open/close switches N14 and N15 are composed of N-MOSs for enhancement operation. 1st. Second open/close switch N14. The sources of N15 are commonly connected to the P-wells of this transistor.

Also, 1st. Second open/close switch N14. N15 P-
) are the sources of the inverters 112, 113 that control the first . They are connected to the source side electrodes of the second open/close switches N14 and N15, respectively.

The source electrode of the first open/close switch N14 is a capacitor C.
It is connected via 1l to the output point of a CMOS inverter Ill arranged to vary the voltage at the other end of the capacitor.

The source of the first on-off switch N14 is connected to the drain of the second on-off switch N15, and the source of the first on-off switch N14 is connected to the drain of the second on-off switch N15.
The source of No. 15 is the output terminal Vout.

f-) of the second open/close switch N15 is connected to the third
is connected to the output point of the inverter 113. The dirt of the third inverter 113 is the first open/close switch N14.
f-).

The source of the N-channel side N13 of the third inverter 113 is connected to the source of the second open/close switch N15. The source of the second open/close switch N15 and the P-well of this transistor are commonly connected, and the so-called 70
The P-well of the first on-off switch N14 is separated from the P-well of the first on-off switch N14.

In addition, Nil to N13. pH~P13 are transistors, respectively; 9. C12 is Conde/S.

-MIN is a voltage input terminal.

The operation of this circuit is as follows: the clock input terminal φ has a high level H
The stain pressure is increased by repeating 10-repel L.

First, the case when the clock input terminal φ is at L level will be explained. Since the input terminal φ is at the 1L level, the f-) voltage of the first on-off switch N14 is the voltage of the inverter 11 connected to the f-) of the first on-off switch N14.
Since the output of No. 2 is at H level, it is in a conductive state. Therefore, the potential of the capacitor C1l connected to the first open/close switch N14 becomes the input voltage (-VIN).

Furthermore, since the output of the inverter Ill is at the H level, the other electrode of the capacitor C1l is at the ground level. In this state, the second open/close switch N
15 is in the off state.

Next, when the clock manual power φ reaches the H level, the first open/close switch N14 changes to f of this first open/close switch N14.
-) Since the voltage becomes equal to the source potential of the second open/close switch N14, the switch is turned off. Then, the output of the inverter Ill, to which the other end of the capacitor C1l connected to the first open/close switch N14 is connected, changes to L level, and therefore becomes -VN.

As a result, the voltage between both electrodes of capacitor C110 is twice (-V
N), the source potential of the first open/close switch N14 becomes -2VN. At this time, the second opening/closing switch N15 becomes conductive, so the voltage of -2VN comes out from the output terminal VoutK.

Therefore, the voltage between the ground and the output terminal is -2VN, which doubles the voltage.

However, in the case of the conventional circuit, the enhancement type open/close switch N14. In order to use N15, in order to input the input voltage -VN to the source side of the open/close switch, that is, the side where the voltage rise is expressed, it must be represented by a transistor whose source and substrate potential are common, and the open/close switch The N-channel transistor of the switch is placed in a P-well structure or equivalent P'' to float the substrate.
There are restrictions that must be made within the layer.

In order to turn the on-off switch into an OFF state, it is necessary to apply a voltage whose P-) voltage of the on-off switch is equal to or lower than the source voltage of the on-off switch plus the threshold voltage.

Therefore, the structure of the on/off switch is that NMO8 is placed in the P-well.
) It has the disadvantage of having to use a floating substrate structure that composes a transistor, and the configuration of the inverter that controls this on/off switch also has the disadvantage that the r- Since the off-state potential applied to the inverter must satisfy the above conditions, the source of the inverter must be in common proximity with the source of the on/off switch.

Such a circuit configuration has the disadvantage that the voltage conversion efficiency of the capacitor is poor due to the parasitic capacitance of the inverter.

In addition, when opening and closing is performed using an enhancement type MOS (MOS) run source, for example, N
Channel MO8) When using the Lansostar open/close switch, as shown in FIG. 1, it is possible to obtain only twice the negative voltage, but not twice the positive voltage.

Semiconductor integrated circuits constructed with general KN channel MO8) run stars often use a positive voltage with respect to ground, which has the drawback of making it difficult to use in conventional circuits.

Conversely, if you try to increase the positive voltage using an N-channel enhancement type switch, the threshold voltage VT of the switch will increase from the input voltage to VT.
Since only the value obtained by subtracting the voltage is input through this on/off switch, the voltage increase efficiency has to be reduced.

In addition, in such usage, the threshold voltage VT
Variations in the value due to dependence on the wafer process directly affect the voltage increase efficiency, which is undesirable because it is difficult to obtain a constant value for the voltage used due to device characteristics.

Furthermore, there is a method of controlling the f-) voltage of the open/close switch with a higher voltage, but generally speaking, when increasing the voltage and using it, there is no voltage higher than the power supply voltage, so It is necessary to provide another voltage booster circuit to set the r-to voltage of this on/off switch, which results in wasteful circuit construction. In this way, enhancement type M
O8) The voltage booster circuit using the Lansostar had many drawbacks.

(Objective of the Invention) The present invention has been made to eliminate the above-mentioned drawbacks of the conventional technology. The purpose is to provide a booster circuit.

(Structure of the Invention) The voltage booster circuit of the present invention is a depression type MO8)
When a 1H" level is applied to the first open/close switch using a transistor, it is turned on and the drive transistors of the first and second inverters are turned on to ground the output terminal of each inverter, and the first open/close switch is turned on. When the power supply voltage on the output side is set to the same potential as the voltage at the voltage input terminal, and the 1L'' level is applied to the first on/off switch, the first on/off switch is turned off and the first on/off switch is turned off. At the same time, the drive transistor of the second inverter is turned off, a power supply voltage is generated at the output terminal of the first inverter, and a voltage twice the power supply voltage is generated at the output side of the first open/close switch. ) A second on-off switch using a transistor is turned on to obtain twice the power supply voltage at the output terminal.

(Example) Hereinafter, an example of the voltage booster circuit of the present invention will be described based on the drawings. FIG. 2 is a circuit diagram of one embodiment. In this embodiment, a case of a voltage doubler circuit is shown. II and I2 in the figure are inverters having an N-channel MO8 E/l (enhancement/depression) MO8 configuration. D1-D4 are depression type MO8) ransosta, and El.

E2 is an enhancement type MO8) run star.

Depression type MO8) Lanzosta D1 and D2 are the first. It serves as a second open/close switch.

Further, CI and C2 are capacitors. φ is a clock input terminal, which is operated by a clock driver (not shown).

vIN is a voltage input terminal. Enhancement WMO
8) Transistor El, E2゜depression type MO8)
The P-to electrode of transistor D1 is connected to clock input φ. Depression type MO8) Lansostar D1
The drain of is connected to the voltage input terminal VIN. The source of the depletion type MO8) transistor D1 is connected to one electrode of the capacitor C1, and is also connected to the drain of the depletion type MO8) transistor D4 of the inverter (2). The other end of the capacitor CI is connected to the output terminal of the inverter 1.

The drain of the depression type MO8) transistor D2 is connected to the source of the depression type MO8) transistor D1.
The source of No. 2 is the output terminal Vout. A capacitor C2 is added to hold the output terminal voltage, and is connected between the output terminal Vout and ground.

In impertae 1, enhancement type MO8)
Lansosta E1 drain and depression WMO8)
The source of the transistor D3 serves as the output terminal of the above-mentioned inverter II, and the depletion type MO transistor D3 (P-) is connected to its source, and the power supply voltage VDD is applied to its drain.

The source of the enhancement transistor E2 of the inverter I2 is grounded, and the drain, together with the source of the depletion type MO8) transistor D4, appears as an output terminal. Depression type MO8) transistor D4
P-) of is connected to its source.

Next, regarding the operation of the voltage external pressure circuit of the present invention configured as described above, the case where the clock input terminal φ is 1H'' (applied voltage VDD level) and the case where it is 1L'' (GND level) will be explained.
Each state will be explained separately.

First, when the clock input terminal φ is at H level, the driving MO8) transistors of inverters 1 and I2, that is, the enhancement type MO8) transistors El and E2 are turned on, and their respective output terminals are brought to the GND (ground) level. ing. Depression WMO8) as the first open/close switch
level, this depletion type MO8) transistor D1 is in a conductive state, and since its source potential is a depletion type transistor, VIN=VDD is input to its tt level.

Also, since the enhancement type MO8) transistor E2 is on and the output terminal of the inverter I2 is at the GND level, the depletion type MO8) transistor E2 as the second open/close switch is
O8) Since the y-to potential of transistor D2 is at L'' level, it is in the off state.

Next, when the clock input terminal φ is inverted and reaches the L level, the depression as the first open/close switch: M/WMO
8) The run source D1 is turned off.

In addition, the drive MO8) transistor of the inverter Il and I2, that is, the enhancement type MO8) transistor E
1 and E2 are also turned off. As a result, the power supply voltage VDD is outputted to the output terminal of the inverter 1.

As a result, the electrically floating state of depletion s:zJ
MO8) The source potential of transistor D1 is raised to twice the VDD potential.

In addition, since the drain of the depletion type MOS transistor D4 of the impermeable MOS transistor D4 is connected to the source of the depletion type MOS transistor D1 serving as the first open/close switch, the output voltage of the imperpere 2 is twice as high as V.
DD is output, and as a result, the depression type MO8) running star D2 as the second opening/closing switch is turned on, and twice the VDD voltage appears at the output terminal Vout. The voltage is charged to capacitor C2 and stabilized.

Furthermore, when the clock input terminal φ is inverted and becomes 1H' level, the depression type MO8) running star D2 as the second open/close switch is not in the off state, and the VD is doubled.
D voltage is held on capacitor C2.

If pulses are continuously input to the clock input terminal φ as described above, twice the VDD voltage is always maintained at the output terminal Vout.

Figure 3 shows the voltage rise timing when the operation starts at t=to. Figure 3 (a) shows the clock input to the clock input terminal φ, and Figure 3 (b) shows the output. The voltage (2VDD) at the terminal Vout, FIG. 3(e) shows the power supply voltage VDD, and FIG. 3(d) shows the GND potential.

In addition, Fig. 4 is a schematic diagram of the r-) potential suitable for this invention at f-)L and H times of a depression type MO8) transistor, and Fig. 4(a) is a schematic diagram of the r-) potential suitable for this invention at f-)L and H times.
4(b) is a potential diagram at time t1 in FIG. 3, where the potential ψGL under the dirt when φ=1L" is lower than ψWIN in terms of potential. Figure 4(c) shows the potential diagram at time t2 in Figure 3. When φ=H, ψvIN and ψ
. 1□ indicates that the selection is made to be higher.

On the other hand, in Fig. 15(a), when the P−) potential ψGI of the depletion type MO8) transistor is ψ7□, which is also large (
The schematic structure of ψvIN <ψGL) is shown in FIG.
b) shows that if ψWIN <ψG when φ=L, ψWIN will enter the hole on the source side and the voltage will not be able to rise.

Therefore, the threshold voltage conditions for the depletion type MO8) runster that can be used for the open/close switch of this embodiment are as follows:
As shown in FIG. 4(b), when the dart potential of the open/close switch is L, the input voltage becomes a depletion type transistor whose voltage is below a value such that the dart potential of the open/close switch becomes low.

As explained above, the above embodiment does not require a floater substrate layer like the conventional circuit, and can be formed on the same substrate.

In addition, since the open/close switch is composed of a depletion type MOS transistor, the dart voltage of the depletion type MO8) transistor D1 as the first ll'1 switch needs to be a voltage-converted pulse. Since the voltage can be effectively transferred to the source side, one inverter for controlling the open/close switch can be removed compared to the conventional circuit configuration.

Furthermore, for example, if the first open/close switch is an enhancement type element, its source side potential drops by the voltage of the MOS transistor, resulting in a decrease in voltage raising efficiency.

Furthermore, the threshold level of a MOS transistor is strongly dependent on the wafer process, and the voltage increase value after device fabrication varies depending on the wafer process, which often results in deterioration of device characteristics. These drawbacks have been solved by using a depression type MO8) run star.

In addition, the advantage of this is that, as can be understood by considering the voltage increase process, the voltage increases by storing charge in the capacitance of the electrode (here, the source side of the depletion type MO8 transistor D1) where the voltage is being increased. Therefore, the stray capacitance of the inverter connected to the voltage-increasing capacitor CIK displaces the electric charge and reduces the voltage-increasing efficiency. Therefore, compared to a conventional circuit that uses two stages of inverters to obtain a doubled voltage, this embodiment can obtain a doubled voltage with only one stage.
FIG. 6 shows another embodiment of the present invention in which the voltage increase efficiency can be increased, and is an example in which the circuit is constructed using a CMOS configuration. PI, P2 are P-MOS) run stars, Nl
, N2 are enhancement type NMO8) transistors, and DI and D2 are depletion type NMO8) transistors, which serve as open/close switches. The circuit operation is similar to the first embodiment.

(Effects of the Invention) As described above, according to the voltage booster circuit of the present invention, when the clock input terminal is at H level, the first open/close switch is turned on and the driving transistors of the first and second inverters are turned on. to set the output terminal of each inverter to ground potential, and set the output side of the first open/close switch to the same potential as the power supply voltage and the voltage of the voltage input terminal, and when the clock input terminal is 1L11/bell, the first open/close switch is set to ground potential. At the same time as turning off the first. When the drive transistor of the second inverter is turned off and a power supply voltage is generated at the output terminal of the first inverter, a voltage twice the power supply voltage is generated at the output side of the first open/close switch. At the same time, the second on/off switch is turned on to obtain twice the power supply voltage at the output terminal, so fewer circuit elements can be configured in a single channel, the voltage increase efficiency is high, and the increase accuracy is high. Good.

Accordingly, since it can be integrated on-chip in a light-load semiconductor integrated circuit, it can be used as a voltage booster circuit for small, lightweight, low-voltage COD sensors and other integrated circuits.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of a conventional voltage booster circuit, FIG. 2 is a circuit diagram of an embodiment of the voltage booster circuit of the present invention, and FIG. 3 is a timing diagram for explaining the operation of the voltage booster circuit of FIG. 2. Charts, Figures 4(a) to 4(c) and 5(a)
and FIG. 5(b) are schematic diagrams of L level and H level of a depletion type MOS transistor applied to the above voltage booster circuit, respectively, and FIG. 6 shows another embodiment of the voltage booster circuit of the present invention. It is a circuit diagram. Engineering 1...first inverter, I2...second inverter, El, E2...enhancement) WMO8) transistor, D1-D4...depression type MOS transistor, CI, C2...capacitor , VIN...
・Voltage input terminal, φ...Clock input terminal, Vout
...Output terminal. Patent Applicant Oki Electric Industry Co., Ltd. Figure 6 Procedural Amendments Showa 5 Rev. June 12th Kazuo Wakasugi, Commissioner of the Japan Patent Office 1. Indication of the case 1982 Patent Application No. 176242 2. Name of the invention Voltage booster circuit 3. Relationship with the case of the person making the amendment Special fraud Applicant (029) Oki Electric Industry Co., Ltd. 4. Agent 5. Date of amendment order Showa 1999, month, day (spontaneous) 6. Details of the invention in the specification to be amended. As shown in the explanation column, Drawing 7, and Attachment 7, Contents of the amendment 1) "Approach" in line 8 on page 7 of the specification is corrected to "connection." 2) In Figure 2 of the drawing, the code rc4i is corrected to "C1" as shown in red on the attached sheet. Ward E Map 2

Claims (2)

[Claims] (1) Depletion type MO8) The first opening/closing which is turned on when the clock signal applied to the r-t of the transistor is at H level, outputs the input voltage to the multi-output side, and is turned off when this clock signal is at 1L'' level. a switch, and a first switch that outputs a ground potential when the first on-off switch is on and outputs a power supply voltage when the first on-off switch is off, thereby doubling the power supply voltage on the output side of the first on-off switch. an inverter, and a second inverter that outputs a ground potential when the first on-off switch is on and a power supply voltage twice as high as that on the output side of the first on-off switch is applied to the output side when the first on-off switch is off. When the first opening/closing switch is turned on, it is turned off, and when the first opening/closing switch is turned off, it is turned on.
A voltage booster circuit comprising a second open/close switch using a depletion type MOS transistor that generates twice the power supply voltage at the output terminal, and a capacitor that maintains the power supply voltage twice that of the output terminal. (2) When the dirt input voltage of the depletion MO8 type transistor is at an off level, the potential immediately below this f-t is lower than the input terminal potential. Voltage boost circuit.