JPS6073235U - 半導体装置 - Google Patents

半導体装置

Info

Publication number
JPS6073235U
JPS6073235U JP1983165472U JP16547283U JPS6073235U JP S6073235 U JPS6073235 U JP S6073235U JP 1983165472 U JP1983165472 U JP 1983165472U JP 16547283 U JP16547283 U JP 16547283U JP S6073235 U JPS6073235 U JP S6073235U
Authority
JP
Japan
Prior art keywords
semiconductor device
semiconductor equipment
pads
substantially circular
abstract
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1983165472U
Other languages
English (en)
Inventor
萩本　英二
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP1983165472U priority Critical patent/JPS6073235U/ja
Publication of JPS6073235U publication Critical patent/JPS6073235U/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/117—Shapes of semiconductor bodies
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/541—Dispositions of bond wires
    • H10W72/5449—Dispositions of bond wires not being orthogonal to a side surface of the chip, e.g. fan-out arrangements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/931—Shapes of bond pads
    • H10W72/932—Plan-view shape, i.e. in top view
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/754—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked insulating package substrate, interposer or RDL

Landscapes

  • Wire Bonding (AREA)
  • Die Bonding (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。

Description

【図面の簡単な説明】
第１図は本考案の第１実施例の上面図であって、キャビ
ティ部のみ示したものである。第２図は第１図に示す実
施例のＡ−Ａ’断面の要部拡大図である。第３図は本考
案の第２の実施例を示す上面図である。ここに、 １・・・・・・パッケージ、２・・・・・・半導体素子
搭載部、３・・・・・・半導体素子、４・・・・・・半
導体素子のパッド、５・・・・・・ボンディングワイヤ
ー、６・・・・・・パッケージの内部リード、７・・・
・・・外部リード、８・・・・・・金属板、９・・・・
・・放熱スタッド、１０・・・・・・封止面、１１・・
・・・・絶縁用セラミックス。

Claims (1)

    【実用新案登録請求の範囲】
  1. 半導体素子上のパッドを略円形に配列し、かつ、半導体
    装置用パッケージの該半導体素子搭載部の体刑が前記半
    導体素子のパッドと同心円状に略円形となっていること
    を特徴とする半導体装置。
JP1983165472U 1983-10-26 1983-10-26 半導体装置 Pending JPS6073235U (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1983165472U JPS6073235U (ja) 1983-10-26 1983-10-26 半導体装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1983165472U JPS6073235U (ja) 1983-10-26 1983-10-26 半導体装置

Publications (1)

Publication Number Publication Date
JPS6073235U true JPS6073235U (ja) 1985-05-23

Family

ID=30362516

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1983165472U Pending JPS6073235U (ja) 1983-10-26 1983-10-26 半導体装置

Country Status (1)

Country Link
JP (1) JPS6073235U (ja)

Similar Documents

Publication Publication Date Title
JPS60129136U (ja) 半導体装置
JPS6120051U (ja) 半導体装置の外囲器
JPS6081652U (ja) 樹脂封止型半導体装置
JPS585347U (ja) 樹脂封止型半導体装置
JPS5840843U (ja) 樹脂封止型半導体装置
JPS5933254U (ja) 半導体装置
JPS59192846U (ja) 半導体装置
JPS6013737U (ja) 半導体集積回路装置
JPS5972737U (ja) 半導体装置
JPS5822751U (ja) 半導体集積回路装置
JPS5846449U (ja) 半導体装置
JPS6196547U (ja)
JPS5958941U (ja) 半導体装置
JPS60153543U (ja) 半導体装置用リ−ドフレ−ム
JPS6094836U (ja) 半導体装置
JPS6068654U (ja) 半導体装置
JPS6112249U (ja) 半導体装置
JPS6061729U (ja) 半導体装置
JPS5965553U (ja) 集積回路装置
JPS5914338U (ja) 混成集積回路
JPS61102049U (ja)
JPS60137435U (ja) 半導体装置
JPS6033437U (ja) リ−ド無しチップキャリヤ構造
JPS61102050U (ja)
JPS60133644U (ja) 集積回路用リ−ドフレ−ム