JPS60737A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To prevent the lowering of dielectric withstand voltage of a gate oxide film by a method wherein a low temperature preparatory heat treatment is performed before a high temperature heat treatment is performed on a double-layer gate. CONSTITUTION:A polycrystalline Si film 3 is formed on the surface of a semiconductor substrate 1 having a gate oxide film 2 and an SiO2 film 8, phosphorus is diffused into the Si film subsequently, and then an MoSi2 film 4 is vapor- deposited thereon. Then, a dry etching is performed on double-layer films 3 and 4, and a gate electrode and a wiring are formed. Subsequently, after preparatory heat treatment has been performed at approximately 600 deg.C for 30min or thereabout in N2 or N2+H2, a high temperature heat treatment is performed at approximately 1,000 deg.C for 30min of thereabout, and the wiring resistance of the double-layer film is lowered. Subsequently, a source and drain region is formed by injecting impurities using the gate electrode of the double-layer film as a mask, and an Al/Si electrode is provided. Then, by performing two stages of heat treatments of low and high temperature, the yield rate of dielectric withstand voltae of the gate oxid film can be improved.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention particularly relates to a method for manufacturing a semiconductor device having low resistance electrodes and wiring including a film made of a metal 2 alloy or a compound thereof such as silicide.

Conventional structure and its problems With the miniaturization of element dimensions and higher integration in MO3O3 type circuit devices, gates and gates using conventional polySt.
The decrease in operating speed due to wiring resistance cannot be ignored. For this reason, the use of high-melting point metal silicide/poly Si double-layer gates and interconnects, which have low resistance, electrical characteristics, and handling in the manufacturing process that are almost the same as poly-Si gates, is an effective way to increase speed. It is a method. In the process of a MOS semiconductor device using such a double-layer gate, heat treatment at approximately 1000"C is required to lower the resistance of the refractory metal silicide itself to a value effective for device characteristics or to form a drain layer. Although it requires a process, this high-temperature heat treatment has the disadvantage that significant leakage occurs in the gate insulating film between the gate electrode and the silicon substrate, and the withstand voltage is almost exhausted.

Conventionally, in order to prevent deterioration of the dielectric strength voltage, a method has been used to increase the thickness of the polySi film forming the lower layer of the two-layer gate. For example, if high melting point metal silicide is M
oSi2. In the case of WSi2, if the film thickness of n+polySt is f 200 nm or more, the specific resistance as a double layer gate will be about 10 even if heat treatment is performed at 1000°C for 30 minutes.
-' (2 cm), and at the same time, it is possible to prevent the breakdown voltage of the gate insulating film from deteriorating substantially.

Even when other high-melting point metal silicides such as Ta512 and TlSi2 are used, breakdown voltage deterioration can be similarly prevented by increasing the polySt film thickness.

However, in order to effectively increase the speed of high-density integrated circuits using double-layer gates and wiring, it is necessary to lower the sheet resistance of the double-layer gate to 1510Ω/■ or less, and therefore the sheet resistance is determined. The film thickness of the high melting point metal silicide 1 must be approximately 200 nm or more. In this way, MOS i2, W S
The film thickness of a double-layer gate using f-based gates with low resistance and no deterioration of gate breakdown voltage is 400 nm or more, and in some cases, it is possible to
This value is larger than the OlySi gate film thickness.

If the gate film is thick, side etching is likely to occur.
The precise microfabricability of the two-layer film is impaired, and the aluminum wiring formed above the gate electrode may be disconnected due to the step difference in the gate electrode due to the thick film, and the anisotropic dry lithography method used to form the wiring may still cause problems. There is a very high probability that a short circuit between wiring lines will occur due to a chipping defect. These drawbacks significantly reduce the manufacturing yield of integrated circuits.

Purpose of the Invention The present invention provides a method for manufacturing a semiconductor device that improves the drawbacks of the above-mentioned conventional example, and aims to completely improve the dielectric strength yield of the gate insulating film and eliminate drawbacks such as disconnections and short circuits. do.

Structure of the Invention In the manufacturing method according to the present invention, a low-temperature heat treatment is applied to the double-layer gate in advance before performing high-temperature heat treatment to reduce the sheet resistance of the double-layer gate and to form a sonis drain layer. be.

DESCRIPTION OF THE EMBODIMENTS FIG. 1 shows a process implementation for manufacturing a MOS transistor. First, a 35 nm thick film was deposited on a silicon substrate 1.
Two gate oxide films are grown (step (a)). Next, a poly Si film 3 of 1100 nm in thickness is formed on the gate oxide film 2 by low pressure CVD or the like, and then Pα film is formed. 90 from the source
Diffusion of phosphorus into the poly St film at o℃
The surface concentration of Si3 is 1 x 1020/cd to 3 x 1020
Aim for an A- grade. Following this, Mo5t24'i
200 nm (step (b)), above 3.
Dry etching using CCu4 or CCF4+02 mixed gas is performed to selectively remove and form a gate electric current. After this, heat treatment was performed for 30 molecules at 600°C in an N2 or N2 + H2 atmosphere, followed by a 10-molecular heat treatment in N2.
A high temperature heat treatment is performed at 00°C for 30 minutes to lower the resistance of the two-layer gate (step (C)). After heat treatment, CV D Si
○2 films 5 f 400 nm thick were formed and then 900 nm thick was formed in N2 again.
℃ for 60 minutes, and seven Afi electrodes for measurement are provided in the contact window 6 opened in the film 5 to complete the process (step (d)
)].

Approximately 400 gate dimensions 25 manufactured according to FIG.
As a result of measuring the breakdown voltage of the gate e-oxide film 2 for a 0 μm x 250 μm MOS capacitor, it was found that although the film thickness of the poly Si film 3 was 1100 nm, it was s MV/cm.
The yield of samples with the above breakdown voltage was 9.o4 or higher, and most of the samples showed a value of 9 MV/Cm, which is a breakdown voltage specific to the oxide film, and it was clear that there was no breakdown voltage deterioration. For a MOS capacitor produced using a conventional manufacturing method that does not undergo preheat treatment at 600°C, the breakdown voltage yield obtained in the same experiment was approximately 60%. Therefore, the production method according to the present invention improves the breakdown voltage yield of the gate oxide film. It can be seen that there is a large effect on

Well, the sheet resistance of this MoSi2/polySi double layer gate is 8-10Ω/gate, which is higher than the conventional n+-pol gate.
The sheet resistance was approximately 1/6 lower than the sheet resistance of the ysi gate.

In the example step (C), the preliminary heat treatment temperature (i760
Although the temperature was set at 0°C, using a temperature of about 6°C to 900°C is also effective in improving the withstand voltage yield. Further, in the example, step (C) was performed. Two heat treatments may be performed after forming the CV D S 102 film 5 in step (d),
It goes without saying that the low-temperature preliminary heat treatment may be carried out after the formation of the gate electrode in step (c) and after the formation of the fCV, D S 102 film 5, which is a high-energy heat treatment for the purpose of lowering the sheet resistance.

FIG. 2 shows an embodiment in which the manufacturing method according to the present invention is applied to a full integrated circuit process of a MoS type integrated circuit. 1 is a semiconductor substrate, 2 is a gate oxide film with a thickness of 35 nm, and 8 is a thick S
102 film (step (a)). 1100 nm of poly Si3 is formed on the entire surface of this semiconductor by LPCVD, etc., and phosphorus is diffused into the poly Si film at 900°C from a Pαn3 source, so that the surface concentration of poly Si3 is 1×10
20/cr/l to 3 X 1 o20/cni. Subsequently, a MoS 12 film 4 f 200 n was formed on the polySt by magnetron sputtering or the like.
(Step (b)) The formed two-layer films 3 and 4 are
is selectively removed by dry etching using a gas such as CCl4+02 to form a gate electrode and wiring on the S102 film 8.

Next, after preliminary heat treatment at 600° C. for 30 minutes in N2 or N2+H2, high-temperature heat treatment at 1000° C. for 30 minutes in N2 is performed to lower the wiring resistance of the two-layer film (step (C)).

After this, the gate electrode consisting of the two-layer film is used as a mask, and the impurities forming the opposite conductivity type to the substrate 1 are added in a total of 1×1015 to 1×
1016/cλ is implanted, source/drain regions 9 are formed, 10 fc of CV D S 102 films are deposited, and heat treatment is further performed for 6Q at 900° C. in N2 (step (d)).

CV D S 102 'Membrane 10 -@ fully opened, 8Q
/Si electrode 7 (i7 is provided to complete the process (process (e)
)).

In this step as well, the preheat treatment temperature may be set at about 600°C to 900°C, as in the above embodiment, and it is possible to perform both preheating, preheating, and high-temperature heat treatment, or only high-temperature heat treatment.
This can be done after D S 102 formation. but,
In order to keep the gate length short and the source/drain junction depth IA'<<, as in the example in Fig. 2, high temperature heat treatment is completed in step (C), and after source/drain formation, heat treatment is performed only at low temperature. It is better to suppress impurity diffusion.

Although the embodiment has been shown for a circuit device including one type of transistor (N-channel or P-channel), the same manufacturing method can be applied to the 0M03 circuit.As mentioned above, the high melting point metal silicide/ pol
The gate oxide film breakdown voltage deterioration phenomenon in the y St two-layer gate structure occurs not only when the silicide is MoSi2, but also when WSi2. TiSi2. This is a common phenomenon when using other silicides such as TaSi2 and high melting point metals such as Mo, W, Ti, Ta, etc., and experiments have shown that suppressing deterioration can be prevented by increasing the thickness of the polySi film. has been done. The melting point of these silicides and high melting point metals,
There is no fundamental difference in thermal properties, such as the eutectic temperature with Si and the reaction mechanism due to heat treatment with polysi are all similar. Therefore, in order to prevent deterioration of the breakdown voltage of the gate oxide film in a gate having a two-layer structure of a silicide other than MoS 12 or a high melting point metal and a thin polySi film, the low temperature according to the present invention is used.

High-temperature two-stage heat treatment is effective.

Effects of the Invention As shown in the examples above, the present invention provides a double-layered gate structure with two-step heat treatment at low and high temperatures.
Even if the ly Si film thickness is thinner than the conventional one, the dielectric breakdown voltage yield of the gate oxide film can be significantly improved. Therefore, according to the present invention, the total film thickness of the two-layer gate can be reduced by reducing the poly-Si film thickness, so that the side etching of the two-layer gate itself can be reduced, and microfabrication is facilitated. It is possible to eliminate defects such as disconnections and short circuits in the upper aluminum wiring due to the gate film step, and this is effective in improving the manufacturing yield of semiconductor devices.

[Brief explanation of drawings]

FIGS. 1(a)-(d) show a MOS structure according to the method of the invention.
Cross-sectional view of the process of manufacturing a capacitor, Figure 2 (,) to (
, ) are cross-sectional views of the process of manufacturing an MO3 type integrated circuit according to the method of the present invention. 1... Semiconductor substrate, 2... Gate oxide film, 3... Poly Si, 4 =...M
oSi2.5,10---CV DS 102 film, 6... Contact window, 7... Aluminum electrode, 8... Thick Si02 film, 9...・Source-Drain 0 Name of agent: Patent attorney Toshio Nakao and 1 other person 1st
Figure 2 Figure 2

Claims (2)

[Claims] (1) A semiconductor film is entirely deposited on an insulating film formed on a semiconductor substrate, and at least one kind of a metal or a compound of the metal and a semiconductor is deposited on the semiconductor film to form a two-layer film. a step of selectively removing the two-layer film to form a pattern, and a heat treatment at the highest temperature after forming the two-layer film? A method for manufacturing a semiconductor device, comprising the step of performing heat treatment at a temperature lower than the above temperature before performing heat treatment. (2) The semiconductor film is polycrystalline silicon, and the metal and the compound of metal and semiconductor are high melting point metals. 2. The method of manufacturing a semiconductor device according to claim 1, wherein the silicide is a high melting point metal silicide.