JPS607496Y2 - semiconductor equipment - Google Patents

semiconductor equipment

Info

Publication number
JPS607496Y2
JPS607496Y2 JP19029080U JP19029080U JPS607496Y2 JP S607496 Y2 JPS607496 Y2 JP S607496Y2 JP 19029080 U JP19029080 U JP 19029080U JP 19029080 U JP19029080 U JP 19029080U JP S607496 Y2 JPS607496 Y2 JP S607496Y2
Authority
JP
Japan
Prior art keywords
substrate
cavity
peripheral edge
cap
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP19029080U
Other languages
Japanese (ja)
Other versions
JPS57113449U (en
Inventor
清 垣谷
善精 小林
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP19029080U priority Critical patent/JPS607496Y2/en
Publication of JPS57113449U publication Critical patent/JPS57113449U/ja
Application granted granted Critical
Publication of JPS607496Y2 publication Critical patent/JPS607496Y2/en
Expired legal-status Critical Current

Links

Landscapes

  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Description

【考案の詳細な説明】 本考案は、半導体チップを搭載した基板をキャップ内に
挿入し接着用樹脂材で接着した半導体装置に関するもの
である。
[Detailed Description of the Invention] The present invention relates to a semiconductor device in which a substrate on which a semiconductor chip is mounted is inserted into a cap and bonded with an adhesive resin material.

第1図は本考案に係るプラグ・イン・タイプのパッケー
ジの半導体装置の断面図である。
FIG. 1 is a sectional view of a semiconductor device in a plug-in type package according to the present invention.

1はセラミックの基板で表面に半導体チップ2が搭載さ
れ、裏面に外部端子3が垂直に設けられている。
A ceramic substrate 1 has a semiconductor chip 2 mounted on its front surface and external terminals 3 vertically provided on its back surface.

半導体チップ2はワイヤー4により基板1の表面の内部
リード5を介して外部端子3に導通している。
The semiconductor chip 2 is electrically connected to an external terminal 3 via a wire 4 and an internal lead 5 on the surface of the substrate 1 .

6はキャップでその空洞は基板1の外周に略一致してお
り、基板1をその空洞内に挿入し接着用の樹脂材7によ
り接着することにより半導体チップ1は封止される。
Reference numeral 6 denotes a cap whose cavity substantially coincides with the outer periphery of the substrate 1, and the semiconductor chip 1 is sealed by inserting the substrate 1 into the cavity and bonding it with an adhesive resin material 7.

ところでこの接着か、基板1とキャップ6との間にエポ
キン系樹脂材を置き、高温状態にして樹脂材を軟化せし
め、基板1の自重又は基板1への荷重により基板1をキ
ャップ6の空洞内に挿入し沈み込ませて行なっている。
By the way, by this adhesion, an Epoquin resin material is placed between the substrate 1 and the cap 6, the resin material is softened in a high temperature state, and the substrate 1 is moved into the cavity of the cap 6 due to the weight of the substrate 1 or the load on the substrate 1. This is done by inserting it into the tube and letting it sink.

その場合生じる問題として、各部品の寸法のばらつき、
基板1の空洞内への沈み込み量のばらつき及び樹脂材の
量のばらつき等により、第1図に示す8の如き樹脂材の
未充填や9の如き外への流れ出しが生じることがある。
Problems that arise in this case include variations in the dimensions of each part,
Due to variations in the amount of sinking of the substrate 1 into the cavity, variations in the amount of the resin material, etc., the resin material may not be filled as shown in 8 in FIG. 1, or may flow out as shown in 9.

特にキャップ6の空洞周囲と基板1の外周とは略一致し
といるための前記の種々のばらつきの調整は非常に困難
なものである。
In particular, it is very difficult to adjust the various variations described above so that the circumference of the cavity of the cap 6 and the outer circumference of the substrate 1 substantially coincide with each other.

そこで本考案は、前述にばらつきが少々あっても樹脂材
の未充填が流れ出しが生じないような新規な構造を提供
することを目的とし、その特徴は、表面に半導体チップ
が搭載され裏面に垂直に外部端子が設けられた基板と、
該基板の外周に略一致する空洞を有するキャップとを備
えた、該キャップの該空洞内に該基板が挿入され、該空
洞内に充填された接着材により該空洞の入口周縁部と該
基板の裏面側周縁部とが略一致するように接着されてな
る半導体装置において、 前記基板お裏面側周縁部及び又は前記キャップの空洞の
入口周縁部に前記接着材のにげ部を有してなることにあ
る。
Therefore, the purpose of this invention is to provide a new structure in which the unfilled resin material will not flow out even if there is a slight variation in the above.The feature is that the semiconductor chip is mounted on the front surface and the back surface is vertical. a board provided with external terminals;
the substrate is inserted into the cavity of the cap, and an adhesive filled in the cavity connects the entrance periphery of the cavity with the substrate. In a semiconductor device in which a peripheral edge of the back side of the substrate is bonded so as to substantially coincide with the peripheral edge of the back side of the substrate, a stub of the adhesive material is provided at the peripheral edge of the back side of the substrate and/or at the peripheral edge of the entrance of the cavity of the cap. It is in.

以下本考案の壱実施例を図面に従って詳述する。Hereinafter, a first embodiment of the present invention will be described in detail with reference to the drawings.

第2図は本考案の一実施例を示す部分断面図である。FIG. 2 is a partial sectional view showing an embodiment of the present invention.

aは基板1の裏面側の周縁部に接着用樹脂材のにげ部1
0を設けた例である。
a is a ridged part 1 of the adhesive resin material on the peripheral edge of the back side of the substrate 1;
This is an example in which 0 is set.

bはキャップ1の空洞の入口周縁部を外側にまげてにげ
部11とした例である。
b is an example in which the peripheral edge of the entrance of the cavity of the cap 1 is bent outward to form a ridged portion 11.

もちろんa、bの両方を施こしてもよい。Of course, both a and b may be performed.

この様に基板1の裏面側の周縁部及び又はキャップ1の
空洞の入口周縁部にげ部10゜11を設けることにより
、前述した種々のばらつきが少々あっても接着用樹脂材
7の未充填や流れ出しは生じない。
In this way, by providing the stubs 10° 11 at the peripheral edge of the back side of the substrate 1 and/or at the peripheral edge of the entrance of the cavity of the cap 1, even if there are slight variations in the various types described above, the adhesive resin material 7 can be prevented from being unfilled. No leakage occurs.

以上説明した様に本考案によれば接着用樹脂材7の未充
填が流れを防止することができ、製品の信頼性を向上す
ることができる。
As explained above, according to the present invention, the unfilled adhesive resin material 7 can be prevented from flowing, and the reliability of the product can be improved.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は従来の半導体装置の断面図、第2図a、bは本
考案の一実施例を示す部分断面図である。 図中、1・・・・・・基板、2・・・・・・半導体チッ
プ、3・・・・・・外部端子、6・・・キャップ、7・
・・・・・接着材、10.11・・・・・・にげ部。
FIG. 1 is a sectional view of a conventional semiconductor device, and FIGS. 2a and 2b are partial sectional views showing an embodiment of the present invention. In the figure, 1...Substrate, 2...Semiconductor chip, 3...External terminal, 6...Cap, 7...
...Adhesive material, 10.11...Negative part.

Claims (1)

【実用新案登録請求の範囲】 表面に半導体チップが搭載され裏面に垂直に外部端子が
設けられた基板と、該基板の外周に略一致する空洞を有
するキャップとを備え、該キャップの該空洞内に該基板
が挿入され、該空洞内に充填された接着材により該空洞
の入口周縁部と該基板の裏面側周縁部とが略一致するよ
うに接着されてなる半導体装置において、 前記基板の裏面側周縁部及び前記キャップの空洞の入口
周縁部に前記接着材のにげ部を有してなることを特徴と
する半導体装置。
[Claims for Utility Model Registration] A substrate having a semiconductor chip mounted on its front surface and external terminals provided vertically on its back surface, and a cap having a cavity that substantially coincides with the outer periphery of the substrate; In a semiconductor device, the substrate is inserted into the cavity and bonded with an adhesive filled in the cavity so that the peripheral edge of the entrance of the cavity and the peripheral edge of the back side of the substrate substantially coincide with each other, the back side of the substrate A semiconductor device characterized in that the semiconductor device has a stub of the adhesive on a side peripheral edge and an entrance peripheral edge of the cavity of the cap.
JP19029080U 1980-12-29 1980-12-29 semiconductor equipment Expired JPS607496Y2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP19029080U JPS607496Y2 (en) 1980-12-29 1980-12-29 semiconductor equipment

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP19029080U JPS607496Y2 (en) 1980-12-29 1980-12-29 semiconductor equipment

Publications (2)

Publication Number Publication Date
JPS57113449U JPS57113449U (en) 1982-07-13
JPS607496Y2 true JPS607496Y2 (en) 1985-03-13

Family

ID=29994658

Family Applications (1)

Application Number Title Priority Date Filing Date
JP19029080U Expired JPS607496Y2 (en) 1980-12-29 1980-12-29 semiconductor equipment

Country Status (1)

Country Link
JP (1) JPS607496Y2 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5386910B2 (en) * 2008-09-26 2014-01-15 株式会社デンソー Electronic circuit equipment

Also Published As

Publication number Publication date
JPS57113449U (en) 1982-07-13

Similar Documents

Publication Publication Date Title
US5994772A (en) Semiconductor package
JPS5827934U (en) semiconductor equipment
JPS55165661A (en) Semiconductor device
JPH0142344Y2 (en)
JPH0295246U (en)
JPS5821180Y2 (en) semiconductor equipment
JPH0366150A (en) Semiconductor integrated circuit device
JPH04168753A (en) Semiconductor device
JP2841831B2 (en) Chip carrier
JPH0215392Y2 (en)
JPS63187330U (en)
JPS63240034A (en) Resin sealing metal mold for semiconductor module
JPS5998650U (en) Resin-sealed module
JPS61182036U (en)
JPS617045U (en) Lead frame for semiconductor integrated circuits
JPS5933254U (en) semiconductor equipment
JPS6169850U (en)
JPH0474458U (en)
JPS61125054U (en)
JPS63108641U (en)
JPS59103446U (en) semiconductor equipment
JPS5822749U (en) Package for semiconductor devices
JPS5999498U (en) Taping structure of semiconductor device
JPS5994447A (en) Glass-sealed type semiconductor device
JPS6076040U (en) semiconductor equipment