JPS60769A - Manufacturing method of semiconductor memory - Google Patents

Abstract

PURPOSE:To realize an ROM of a small required area by isolating the source and drain regions of an MOS transistor from the gate region, and forming an impurity region in the isolation region. CONSTITUTION:The sources 1, 7 and the drains 2, 8 of the MOS transistor are isolated from the gates 6, 12. Regions 3, 4 having the same conductivity type of the source and drain regions 1, 2, 7, 8 or regions having the different conductivity type are formed in the isolation regions between the gates 6, 12 and the source and drain regions 1, 2, 7, 8, respectively. In such a manner, memory information is written in by the selection of the kind of the conductivity type of impurity regions formed in the isolation regions between the source and drain regions 1, 2, 7, 8 and the gate regions 6, 12.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a semiconductor memory, and more specifically to a read-only memory (Read Qn) that is highly integrated and capable of high-speed reading.
D'Memory (hereinafter referred to as ROM).

[Background of the invention]

ROM uses one MOS transistor for one pit of memory, so the number of components per bit is
It has the smallest amount of memory among various types of memory and is suitable for high integration.

In addition, since the arrangement of devices is regular, LSI
It also has the advantage of requiring less design man-hours, and is widely used in the logical configuration of highly integrated microcomputers.

Therefore, it is clear that reducing the required area of the memory cells that make up each pin of a ROM and reducing parasitic capacitance and resistance would be extremely effective in increasing the integration and speed of LSIs. .

To write memory information to the memory cells of the ROM,
Although there are various methods, it is preferable to write data near the end of the manufacturing process of a highly integrated ROM because the required manufacturing time and the time required to depack the ROM in which memory information has been written will be shorter.

That is, the ROM can be completed in a short time by forming the ROM to a near-complete state and writing memory information in the final or near-final process.

However, in the conventional R, OM, memory information is written depending on whether a thin oxide film or a thick oxide film is formed under the gate electrode of the MOS transistor. Such writing is RO
Since this is done in the initial process of M manufacturing, there is a problem in that it takes a long time for manufacturing and depacking.

In addition, without increasing the required area of memory cells,
There has been a strong demand for a ROM with high integration density that allows memory information to be written.

[Purpose of the invention]

SUMMARY OF THE INVENTION An object of the present invention is to solve the above-mentioned conventional problems and to provide a semiconductor memory in which memory information can be written in the final or near-final process and which can be highly integrated.

[Summary of the invention]

In order to achieve the above object, the present invention separates the source and drain regions of the MOS transistors constituting the memory cell of the fLOM from the gate region, and in the separation region between the two, Information is written by forming impurity regions having opposite conductivity types.

[Embodiments of the invention]

Example 1 The cross-sectional structure of a ROM memory cell according to the present invention is shown in FIGS. 1 and 2. It goes without saying that there is an insulating film between the gate electrode and the substrate, but for ease of understanding, each drawing is shown schematically, and explanations of the present invention such as the gate insulating film are shown. Portions not directly related to the above are omitted from illustration.

As is clear from FIGS. 1 and 2, the source, drain 1.2 and 7.8 of the whalebone transistor are separated from the gates 6 and 12, respectively, and the source and drain regions 1, 2, 7.8 are separated from the gates 6 and 12, respectively. Regions 3 and 4 with the same conductivity type or regions 9 with different regions. 1O are formed in the isolation regions between the gates 6.12 and the sources and drains 1, 2, and 7.8, respectively.

As shown in FIG. 1, when the impurity regions 3 and 4 formed in the isolation region have the same conductivity type as the sources 1 and 2, by applying a voltage to the gate electrode 6, , a current flows between the source and drain 1°2.

On the other hand, as shown in FIG. 2, the conductivity type of the impurity regions 9 and 10 formed in the isolation region is
．． If the substrate 11 is different from the gate electrode 8, no current will flow even if a voltage is applied to the gate electrode 12.

Therefore, in the R, OM according to the present invention, memory information can be written by selecting the conductivity type of the impurity region formed in the isolation region between the north, drain, and gate regions. will be carried out.

Writing information through the formation of such impurity regions can be performed in the latter half of the ROM manufacturing process, as described later, so the time required for device manufacturing and debugging can be significantly shortened. It is possible.

Furthermore, as is clear from the planar structure shown in Figure 3,
Memory information writing region 16.17 formed between source and drain regions 13.14 and gate electrode 15
can be made as small as the manufacturing process allows, so it is possible to form a memory cell with the minimum feature size achievable in the process.

Therefore, not only can extremely high integration density be achieved, but parasitic capacitance and parasitic resistance can also be reduced, and high speeds can be achieved.

Embodiment 2 FIG. 4 shows an example of a method for writing memory information into a ROM according to the present invention, and is an example when applied to a one-channel type ROM.

First, as shown in FIG. 4(a), the impurity concentration lQ''
n shadow area with ~10” cm-”22.23
The n li type source and drain regions 19 and 20 and the gate electrode 21 are formed so as to be interposed between the two.

P-type impurities are introduced into the n-shaded regions 22 and 23 of only the MOS transistors of the ROM cells in which memory information is to be written, using well-known means such as ion implantation, as shown in FIG. 4(b). , impurity concentration 10'6~io
A p shadow region 24.25 of "crn-" was formed.

Note that if the p-type impurity is introduced deeper than the source and drain regions 19°20 by ion implantation using the gate electrode 21 and field oxide film 28 as a mask, the result will be as shown in FIG. 4(C). A ROM with a similar structure is formed.

Embodiment 3 FIG. 5 shows another method of writing memory information into a ROM according to the present invention.

First, as shown in FIG. 5(a), n0 type source and drain regions 19, 20
are formed apart from the gate region 21. Introducing n-type impurities from 10'6 to 101' into the region between the source and drain regions 19 and 20 and the gate electrode 21 of the MOS transistor of the ROM cell in which memory information is to be written.
As shown in FIG. 5(b), n-shaded areas 29 and 30 were formed.

In the MOS transistor shown in FIG. 5(a), even if voltage is applied to the gate electrode 21, the source and drain 19.
It does not flow between 0. However, the MOS shown in FIG. 5(b)
) In the case of a transistor, by applying a voltage to the electrode 2, a current flows between the source and the drain 19, 20, so written information can be detected depending on the presence or absence of the flowing current.

Example 4 FIG. 6 shows another embodiment of the invention.

N-type ions 32 are implanted into the exposed portion of the p-type Si substrate 18 via the electrode 21 to form n4-type source and drain regions 19 and 20.

In the obtained MOS) transistor, the ends of the source and drain regions 19.20 are in contact with the gate region, so when a voltage is applied to the gate electrode 21, a current flows between the source and drain regions 19.20. .

However, as shown in FIG. 6(b), if the mask 31 used during ion implantation also covers the sides of the gate electrode 21, the source and drain regions 19', 20' and the gate region will be separated. , in this case, the gate electrode 2
Even if a voltage is applied to 1, the source and drain regions 19'
, 20', no current leaks between them.

That is, in this embodiment, memory information can be easily written simply by changing the mask pattern during ion implantation.

Embodiment 5 This embodiment shows an example in which a region in which memory information is written is formed not by a mask alignment process but by a self-alignment process.

First, as shown in FIG. 7(a), using the gate electrode 21 as a mask, n-type impurities were ion-implanted into the surface region of the p-type Si substrate 18 to form source and drain regions 33 and 34.

Next, as shown in FIG. 7(b), a thickness of 0.5 to 1.
After depositing a photoresist film or insulating film 35 of about 5 μm on the entire surface, a process such as reactive sputtering, etc.
Perform anisotropic etching.

In this way, as shown in FIG. 7(C), the gate electrode 2 of the photoregist or insulating film 36
Leaving the thicker part on one side, the other parts are removed. In this state, n-type impurities are ion-implanted at 10'6 to 10''on-'' to form n1-type source and drain regions 37.3.
form 8.

If the photoresist or insulating film 38 remaining on the sides of the gate electrode 21 is removed, an n-type impurity region 33.3 is formed between the n''' type source and drain regions and the gate electrode 21.
A MOS) transistor with 4 is formed.

To write information, using the gate electrode 21 as a mask, p-type impurities are implanted to compensate for the n-shaded regions 33 and 34.
As shown in FIG. 7(d), the impurity concentration is 10'' to 10
It is sufficient to form a p shadow region 39.40 of 'cm-'.

In this way, even if a voltage is applied to the gate electrode 21, no current will flow between the source and drain 37, 38, and the presence or absence of information writing can be detected.

Also, impurity regions 39.40 where memory information is written
are formed in a self-aligned manner and do not require a mask alignment process, thereby achieving a reduction in the area required for the ROM memory cell and an improvement in the degree of integration.

Example 6 In Example 5 above, ion implantation was performed so as to leave the photoresist or insulating film 36 on the sides of the gate electrode 21 without forming the n shadow regions 33 and 34, and the n0 type away from the gate 21 was implanted. Regions 37, 38 may also be formed.

In this way, it is possible to omit the formation of the p shadow regions 39 and 40 for information writing shown in FIG. 7(d).

Example 7 Another embodiment of the invention is shown in FIG.

As shown in FIG. 8 (ω), after forming the n+ type source, drain regions 19, 20, gate electrode 21, etc., an insulating film 41 made of PEG (, 9 glass) containing n type impurities such as thin film is coated over the entire surface. Form.

As shown in FIG. 8(b), the insulating film 41 is irradiated with a beam 42 such as a CO2 laser that can be absorbed by the insulating film 41.
1 is diffused into the substrate 18 to form n-type impurity regions 43 and 44. Note that instead of heating the insulating film 41, the substrate 18 may be heated to diffuse the n-type impurity.

A feature of this embodiment is that memory information can be written at the final stage of ROM manufacturing, and the time required for ROM manufacturing can be significantly reduced.

〔Effect of the invention〕

As is clear from the above description, according to the present invention, a ROM with a small required area has been realized, and high integration and high speed have become possible.

Furthermore, since memory information can be written at the final or near final stage of the ROM manufacturing process, the time required for ROM manufacturing and debugging can be significantly reduced.

It goes without saying that the present invention is not limited to the above-mentioned embodiments, and that various modifications are possible.

For example, the present invention applies not only to n-channel MO transistors formed in a silicon substrate, but also to p-channel MO transistors.
O8) transistor, SOS (SiliconO”S
aph i re ) or S OI (5il
icon on ℃ ■#5ulator) structure device or Ga
Devices using compound semiconductors such as As as substrates,
Applicable.

Furthermore, the benefits obtained are extremely large, as it can be applied to programmable logic (PLA) and LSI defect relief circuits.

[Brief explanation of drawings]

1 to 3 are diagrams for explaining the present invention in detail, and FIGS. 4 to 8 are diagrams for explaining different embodiments of the present invention, respectively. 1.2,7,8,13,14,19,20,37°38
...Source, drain region, 3, 4, 16° 17.2
2,23,29,30,33,34゜43.44...
n shadow area, 9, 10, 24, 25° 26. 27, 39.
40...p shadow region, 5,11°18...p type silicon substrate, 6,12,15.21...gate electrode, 31
, 35, 36...Mask, 28...Field insulating film, 41...PEG film, 32...n''5 Figure (η) (Thin 1~Otsu Figure (Good 7th CI -) (C) Child (θ-) 1 (rt) Figure (b) Indication of procedural amendment case 1982 Patent Application No. 107675 Name of invention Relationship to semiconductor memory amendment person case Patent applicant name <5ca ) Co., Ltd. Tsukiguchi Standing 袈 い乍 し た Ｇ 訳 桔transportation of the "Detailed Description of the Invention" of the specification subject to personal amendment → ≠ 呵 ← Contents of the amendment 1, No. 8, line 6 of the specification of the present application ""Electrode2" to "Electrode 21"
Correct it to 5. 2. Ibid., page 10, lines 17 to 19, “As shown in Figure 7 (dl...
Show/Good. ” is corrected.

Claims (1)

[Claims] A gate electrode formed on a semiconductor substrate via an insulating film, and at least a source and drain region formed in a surface region of the semiconductor substrate at a distance from the gate region, the gate region and the source and drain regions. Between,
Information is written depending on the conductivity type of the impurity region formed in the J configuration in contact with the source and drain regions or the presence or absence of the impurity region.
A semiconductor memory characterized by #.