JPS60770A - semiconductor equipment - Google Patents
semiconductor equipmentInfo
- Publication number
- JPS60770A JPS60770A JP58107680A JP10768083A JPS60770A JP S60770 A JPS60770 A JP S60770A JP 58107680 A JP58107680 A JP 58107680A JP 10768083 A JP10768083 A JP 10768083A JP S60770 A JPS60770 A JP S60770A
- Authority
- JP
- Japan
- Prior art keywords
- capacitor
- film
- substrate
- dielectric strength
- trench
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
- H10B12/03—Making the capacitor or connections thereto
- H10B12/038—Making the capacitor or connections thereto the capacitor being in a trench in the substrate
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Semiconductor Integrated Circuits (AREA)
- Semiconductor Memories (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
【発明の詳細な説明】
〔発明の利用分野〕
本発明は半導体装置、特に半導体集積回路メモリに係わ
り、その蓄積容量部の平面々積を増大さぜずに良好な大
容量を実現する半導体装置に関する0
〔発明の背景〕
従来の蓄積容量部は平面Si基板上に形成していたので
、半導体集積回路メモリの高集積化・微細化により、占
有できる面積も減少し信号容量が減少してしまう欠点が
あった。信号容量ヲ大きく保つためには絶縁膜の高誘電
率化、薄膜化も一つの方法であるが、最近平面々積を増
大せずにS+基板に溝を堀りその側壁部を利用して実効
面ftを増大させる方法が提案されている。しかしこの
方法で作った溝に熱駿化法により5io2i形成して作
った蓄積容量の絶縁耐圧は1通常の平面に形成したもの
の1膜2程度となってしまう欠点があった。[Detailed Description of the Invention] [Field of Application of the Invention] The present invention relates to a semiconductor device, particularly a semiconductor integrated circuit memory, and relates to a semiconductor device that achieves a good large capacity without increasing the planar area of its storage capacitor. [Background of the Invention] Conventional storage capacitors have been formed on flat Si substrates, so as semiconductor integrated circuit memories become more highly integrated and finer, the area that can be occupied decreases and the signal capacity decreases. There were drawbacks. In order to maintain a large signal capacity, one method is to increase the dielectric constant of the insulating film and make it thinner, but recently it has been found that trenches are dug in the S+ substrate and the side walls of the trenches are utilized without increasing the planar area. A method of increasing the surface ft has been proposed. However, there was a drawback that the dielectric strength of the storage capacitor formed by forming 5io2i in the groove formed by this method by the thermal oxidation method was about 1.2 even if it was formed on a normal plane.
本発明の目的は、Si基板に溝を堀り側壁部を利用した
蓄積容量に於て、絶縁耐圧を損うことなく実効面積増大
に伴なう容量の大容量化を達成する蓄積容量の構造、な
らびにその製造方法を提供することにある。An object of the present invention is to provide a storage capacitor structure that achieves an increase in capacitance due to an increase in effective area without impairing dielectric strength, in a storage capacitor that uses a side wall portion formed by digging a trench in a Si substrate. An object of the present invention is to provide a method for manufacturing the same.
従来は、8i基板に溝を掘ることにより鋭角なエツジ部
分が発生し、以後熱酸化法により5in2膜を形成する
と絶縁耐圧を劣化させていた。Conventionally, sharp edges were generated by trenching an 8i substrate, and when a 5in2 film was subsequently formed by thermal oxidation, the dielectric strength deteriorated.
本発明は、溝の上にまず熱酸化S r 02膜を形成し
1次いで気相成長法によるSi3N4ヲ形成し、最后に
熱酸化法によりSi3N4を酸化する三層絶縁膜構造と
することにより、絶縁耐圧が平面に形成した場合と遜色
のない良好な大容量蓄積容量を実現するものである。The present invention has a three-layer insulating film structure in which a thermally oxidized Sr02 film is first formed on the trench, then Si3N4 is formed by vapor phase growth, and finally Si3N4 is oxidized by thermal oxidation. This realizes a large storage capacity with a dielectric strength comparable to that of a flat structure.
以下1本発明の一実施例を第1図〜第2図を用いて説明
する。An embodiment of the present invention will be described below with reference to FIGS. 1 and 2.
P型10Ω・cm程度のS+基板1上にSiO□膜など
のマスク材2を付け、不必要な部分そホトエツチング法
などで除去して開口する。この後回2に示すようにCC
l2.CF4.SF6などを主成分とするガスを導入し
た平行平板型プラズマエツチング法で 83基板1の所
望の部分に深さ4μm程度のエッチ溝5を形成した。こ
の後マスクとして用いた8i02膜2を除去してSi基
&を露出させる。その後キャパシタ用絶縁膜3¥−形成
する。A mask material 2 such as a SiO□ film is applied on a P-type S+ substrate 1 of about 10 Ω·cm, and unnecessary portions are removed by photoetching or the like to form an opening. As shown in Part 2 below, CC
l2. CF4. Etch grooves 5 with a depth of about 4 μm were formed in desired portions of the 83 substrate 1 by a parallel plate plasma etching method using a gas containing SF6 as a main component. Thereafter, the 8i02 film 2 used as a mask is removed to expose the Si groups &. Thereafter, a capacitor insulating film 3 is formed.
その後減圧OVD法で多結晶si、ir、2形成し、燐
促)ヲ高濃度に添加してキャパシタの電極とした。Thereafter, polycrystalline silicon, ir, and 2 were formed using a low-pressure OVD method, and phosphorus was added at a high concentration to form a capacitor electrode.
キャパシタ用絶縁膜をまず従来法であるS i O膜を
熱酸化法で、約20 nm形成した。この時熱酸化に先
立って、ドライエッチした面の結晶的な損傷や汚染を除
去するために N H40H十H20zの混合液や M
F+HNO3混合液により僅かに8+基板表面を清浄化
し、僅かに除去した。An insulating film for a capacitor was first formed using a conventional method of thermal oxidation to form a SiO film to a thickness of about 20 nm. At this time, prior to thermal oxidation, in order to remove crystal damage and contamination on the dry etched surface, a mixed solution of N H40H and H20z or M
The 8+ substrate surface was slightly cleaned and slightly removed with the F+HNO3 mixture.
また他の絶縁膜形成法として、熱酸化法によりS io
2膜を形成し、その上に減圧OVD法によりSi3N
4膜を形成し、最後にこのS i 3N4膜をH2−〇
□ガス燃焼法により酸化し、8i02/ 8i 3N4
/SiO2の三層構造膜をトータル膜厚20 nm形成
した。In addition, as another method for forming an insulating film, Sio
2 films are formed, and Si3N is deposited on it by low pressure OVD method.
Finally, this S i 3N4 film is oxidized by H2-〇□ gas combustion method to form 8i02/8i 3N4
A three-layer structure film of /SiO2 was formed with a total thickness of 20 nm.
また他の方法としてSi3N4/SiO2の二層構造膜
や、減圧OVD法により形成した8 r 02膜などに
ついても実施した。In addition, other methods such as a Si3N4/SiO2 two-layer structure film and an 8r02 film formed by a reduced pressure OVD method were also carried out.
通常の熱酸化法により形成した5in2膜キヤノくシタ
の絶縁耐圧を測定した。第3図にその結果を示したが、
ここで絶縁耐圧は10nAのリーク電流が流れたときの
電圧で定義した。電極の面積は5.8xlO’μm2で
、エッチ溝を形成しない平面8i基板上に形成したキャ
パシタと、3600個のエッチ溝が形成された8i基板
に形成したキャパシタ(溝型キャパシタ)とを比較して
示した。The dielectric strength voltage of a 5-inch double-film canister formed by a conventional thermal oxidation method was measured. The results are shown in Figure 3.
Here, the dielectric strength voltage was defined as the voltage when a leakage current of 10 nA flows. The area of the electrode is 5.8xlO'μm2, and a capacitor formed on a flat 8i substrate with no etched grooves is compared with a capacitor formed on an 8i substrate with 3600 etched grooves (groove type capacitor). It was shown.
その結果平面キャパシタの絶縁耐圧が18Vであるのに
対して、溝型キャパシタでは約7vと極端に悪くなる。As a result, while the dielectric strength of the planar capacitor is 18V, the dielectric strength of the trench capacitor is extremely poor at about 7V.
一方本発明によるS I Q□/Si3N4/SiO2
三層絶縁膜構造では、第4図に示すように平面キャパシ
タの絶縁膜耐圧が約21Vであるのに対して、溝型キャ
パシタであっても約20Vと、殆んど絶縁耐圧の劣化が
無い。上記の僅かなlV程度の差は。On the other hand, S I Q□/Si3N4/SiO2 according to the present invention
With a three-layer insulation film structure, as shown in Figure 4, the insulation film breakdown voltage of a planar capacitor is approximately 21V, while even a trench capacitor has a dielectric breakdown voltage of approximately 20V, so there is almost no deterioration in insulation voltage. . The above-mentioned slight difference of about lV.
溝型キャパシタの場合、実効的なキャパシタ面積が増加
したためのもので本質的な差ではない。In the case of a trench type capacitor, this is due to an increase in the effective capacitor area and is not an essential difference.
また他の実施例のS t a N 4 / 8 + 0
2の二層膜や減圧気相成長法によるSiO2膜なども、
熱酸化法により形成したSjO□一層膜よりも溝型キャ
パシタの絶縁耐圧は優れてはいるが1本発明の5in2
/5i3N4/ SiO2三層絶に膜構造に優るものは
ない0
以上のように本発明の5in2/ Si3N4/ Si
O2三層絶縁膜構造によれば、溝を堀って形成する溝型
キャパシタのように、8j基板が鋭角に加工されている
ような形状においても、良好な絶縁耐圧を示すので、半
導体メモリ用の蓄積容量として利用すると、非常に効果
大である。In addition, S ta N 4/8 + 0 in other embodiments
2 double layer film and SiO2 film made by low pressure vapor phase growth method, etc.
Although the dielectric strength of the trench capacitor is superior to that of the SjO□ single-layer film formed by thermal oxidation, the 5in2 of the present invention
/5i3N4/ There is nothing superior to the three-layer SiO2 film structure.0 As described above, the 5in2/ Si3N4/ Si of the present invention
The O2 three-layer insulating film structure exhibits good dielectric strength even when the 8J substrate is shaped at an acute angle, such as a trench capacitor formed by digging a trench, so it is suitable for semiconductor memory. It is extremely effective when used as a storage capacity.
第1図および第2図は溝型キャパシタを製作する工程を
示す図、第3図および第4図はそれぞれ従来および本発
明の絶縁耐圧を示す図である。
1、 8+基板
2、 ドライエッチ用マスク8i0□膜3、キャパシタ
絶縁膜
4、燐を添加した多結晶8i
5・ エッチ溝
ラ・叶う
簗・咲 5FIGS. 1 and 2 are diagrams showing the process of manufacturing a trench type capacitor, and FIGS. 3 and 4 are diagrams showing the dielectric strength of the conventional and the present invention, respectively. 1, 8+ substrate 2, dry etching mask 8i0□ film 3, capacitor insulating film 4, phosphorous-doped polycrystalline 8i 5, etch groove, enamel, bloom 5
Claims (1)
設けた蓄積容量において、蓄積容量を形成する絶縁層部
分を、二酸化硅素(8j02)、窒化硅素(S;3N4
) 、二酸化硅素(8j02)より成る三層絶縁膜構造
としたことを特徴とする半導体装置っ1. In the storage capacitor provided in the area including the sidewalls of the trench dug into the silicon substrate, the insulating layer portion forming the storage capacitor is made of silicon dioxide (8j02) and silicon nitride (S; 3N4).
), a semiconductor device characterized by having a three-layer insulating film structure made of silicon dioxide (8j02).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58107680A JPS60770A (en) | 1983-06-17 | 1983-06-17 | semiconductor equipment |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58107680A JPS60770A (en) | 1983-06-17 | 1983-06-17 | semiconductor equipment |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS60770A true JPS60770A (en) | 1985-01-05 |
Family
ID=14465246
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP58107680A Pending JPS60770A (en) | 1983-06-17 | 1983-06-17 | semiconductor equipment |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS60770A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63316465A (en) * | 1987-06-19 | 1988-12-23 | Hitachi Ltd | Semiconductor device and its manufacturing method |
| JPS6480061A (en) * | 1987-09-19 | 1989-03-24 | Hitachi Ltd | Semiconductor integrated circuit device and manufacture thereof |
| US5017982A (en) * | 1988-11-15 | 1991-05-21 | Mitsubishi Denki Kabushiki Kaisha | Capacitor in semiconductor device |
| JP2019029537A (en) * | 2017-07-31 | 2019-02-21 | 株式会社村田製作所 | Capacitor |
-
1983
- 1983-06-17 JP JP58107680A patent/JPS60770A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63316465A (en) * | 1987-06-19 | 1988-12-23 | Hitachi Ltd | Semiconductor device and its manufacturing method |
| JPS6480061A (en) * | 1987-09-19 | 1989-03-24 | Hitachi Ltd | Semiconductor integrated circuit device and manufacture thereof |
| US5017982A (en) * | 1988-11-15 | 1991-05-21 | Mitsubishi Denki Kabushiki Kaisha | Capacitor in semiconductor device |
| JP2019029537A (en) * | 2017-07-31 | 2019-02-21 | 株式会社村田製作所 | Capacitor |
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