JPS6077257A - Multiprocessor system - Google Patents

Abstract

PURPOSE:To obtain a multiprocessor enabled to reduce the overhead of exclusive control by deciding a lock from lock success and an unlocking request, and when there is no lock at the generation of an exception, executing exception processing in stead of lock processing. CONSTITUTION:When a test and lock request circuit 61 applies a test and lock request to a system control device through a common bus 40, lock success or failure is sent as its reply information. The information is inputted to a lock success detecting circuit 62, and when lock success is detected, an adaptor counter 65 counts up +1. An unlocking request is applied to a system control device by an unlocking request circuit 63 through a common bus 40, and when an unlocking request detecting circuit 64 detects the request, the adaptor counter counts up -1. When the contents of the adaptor counter 65 are ''0'', it means that there is no lock by the processor.

Description

DETAILED DESCRIPTION OF THE INVENTION Technical Field The present invention relates to a multiprocessor system that is controlled by a number of processors and a common storage device and that performs lock/unlock exclusive control.

BACKGROUND ART In a multiprocessor system consisting of a plurality of processors and a common storage device, it is necessary to prevent data contents from being destroyed or erroneously changed due to mutual interference caused by simultaneous updating of a database by the plurality of processors. Therefore, it is necessary to have exclusive control over the database. One method of exclusive control is the lock/unlock method, in which a processor locks the part of the database that contains the data it wants to update, and refuses update processing by other processors until the update processing is complete. It is.

In a multiprocessor system that uses exclusive lock/unlock control, when an exception occurs (a situation in which a normal program sequence cannot be executed), data indicating the lock/unlock status is searched and the own processor is locked. If there is an item in the list, it will be unlocked. This unlocking process is necessary to release the resources locked by the process that was interrupted by the exception.

In this way, in a multiprocessor system, processing related to locking is required when an exception occurs, but such processing is essentially unnecessary when nothing is locked when an exception occurs. Moreover, in most cases, no locks are held when an exception occurs, resulting in a large performance penalty.

OBJECTS OF THE INVENTION Accordingly, an object of the present invention is to provide a multiprocessor system in which exception processing can be performed without performing any lock-related processing when there is nothing locked by the own processor when an exception occurs. It is.

Configuration of the Invention The multiprocessor system of the present invention includes: - test and lock request means for making a test and lock request; lock success detection means for detecting that the test and lock request is successful; and an unlock request for making an unlock request. means, an unlock request detecting means for detecting an unlock request, the lock success detecting means detecting a lock success, and the unlock request detecting means detecting an unlock request, so that the processor is locked. and means for holding information for identifying whether or not there is at least one item.

In this way, the present invention can determine whether there is at least one thing locked by the processor.
1 is locked by the processor when the exception occurs
Exception processing can be performed without any lock-related processing when there is no need, and the overhead of exclusive control can be reduced.

Best mode for carrying out the invention The present invention will be described below with reference to drawings of embodiments.

FIG. 1 is a block diagram of a multiprocessor system according to an embodiment of the present invention. The multiprocessor system of this embodiment includes a plurality of common storage devices 10, 11, 12, a plurality of processors 20, 21, 22, and a system control device 8.
0 and multiple common storage devices ffi 10.11
．． The IJ and the system control device 80 are connected by a memory bus 50, and the plurality of processors 20, 21, 22 and the system control device 80 are connected by a common bus 40. The processors 20, 21, and 22 send address information, lock flag information, and lock processor number information to the system control device 80 at the time of a test and lock request.

FIG. 3(a) shows the format of the data (lock flag information and lock processor number information) sent at the time of a test and lock request. number is written on it.

FIG. 3(b) shows the storage format of the data (lock word) of FIG. 8(a) in the common storage device.

Here, the test and lock request means to read all the data (FIG. 3(b)) at the address indicated by the address information,
If the lock flag information V is '0', the lock flag information and lock processor number information are written into the area indicated by the address information, and if the lock flag information V is '1', no writing is performed.

When the successive p-tsk flag information V is %0/F, it is called "one-trick practice success", and when it is '1', it is called "10-trick failure".

FIG. 2 is a block diagram showing part of the configuration of the processors 20, 21, and 22. Test and lock request circuit 61
When the test-and-lock request is sent to the system control device ff80 via the common bus 4o, the system control device 8o sends response information indicating whether the lock was successful or not as reply information via the common bus 40.

This information of lock success and p-tock failure is stored in the lock success detection circuit 62 for a long time, and when "10-tock success" is detected, a +1 count instruction is given to the up/down counter 65. The request circuit 68 sends the unlock request to the system control device 80 via the common bus 4o. When the unlock request detection circuit 64 detects this unlock request, the up/down counter 65 is set to -1.
A count instruction is given. That is, when the up/down counter 65 is in a reset state, that is, 10'', it means that there is nothing locked by the processor, and when the up/down counter 65 is in a set state, that is, it is not '□ II, the processor is locked. means that there is at least one

When an exception is detected by the exception control circuit 66, the interrupter is activated.

The content of the run counter 65 is checked, and when the run counter 65 is in the one-hit state, the current run counter 65 is checked.
An instruction to unlock the locked item is output to the unlock request circuit 68. The process of unlocking what has been locked by the own processor is to sequentially sequentially input the lock words from 0 to n as shown in FIG. and sends an unlock request.

FIG. 4 shows processors 20, 21.
22 is a block diagram showing a part of the configuration of the computer. The control store 71 stores an unlock control microprogram. Control store 71 is given five address numbers from address register 72 . An adder circuit 78 is connected to the address register 72 to add 1 to its contents. The address register 72 has an adder circuit 78
and the content of the branch address field from the branch control circuit 74 are input, and these two inputs are selected by instructions in the sequence control field of the control store 71. The branch address is modified by the contents of this branch address field, allowing complex conditional branching operations.

The microprogram read from the control store 71 is stored in the command register 75, and its output controls various functions of the processor.

According to instructions from the microprogram, the test and lock request circuit 61 connects to the system controller 8 via the common bus 40.
When a test and lock request is issued to 0, ten reports of successful locking and failure of locking are sent from the system control device 80 to the locking success detection circuit 62 via the common bus 40. When lock success is detected by the lock success detection circuit 62, the 7 lip flop 76 is set. An unlock request is sent from the unlock request circuit 68 to the system controller 80 via the common bus 40 according to instructions from the microprogram. When the microprogram issues an unlock instruction to the last lock for its own processor, it issues a reset instruction to the 7 lip flop block 76. When an exception is detected by the exception control circuit 66, the state of the seven lip flops 76 is tested under the instructions of the microprogram;
7 If the lip-flop 76 is in the set state, the microprogram sets the lock word in FIG. 8(t)) sequentially from 0 to n.
If the lock processor number is the same as the own processor number, an unlock instruction is given to the read lock word, and if the flip-flop 76 is in the reset state, control is performed so that no lock-related processing is performed.

FIG. 5 is a flowchart showing an outline of the unlock control routine of the microprogram explained above.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a multiprocessor system according to an embodiment of the present invention, FIG. 2 is a block diagram of an embodiment of a processor constituting the present invention, and FIG. 8(a) is a block diagram of a multiprocessor system according to an embodiment of the invention. 8(b) is a diagram showing the storage format of the lock word in the common storage device; FIG. 4 is a block diagram of another embodiment of the processor constituting the present invention; FIG. Is it unlocked? It is a flowchart of the A11 program. 10, IL 12: Common storage, 20, 21.2
2: Processor, 80 System control device, 40: Common bus, 50: Memory bus, 61: Test and lock request circuit, 62: Lock success detection circuit, 68: Unlock request circuit, 64: Unlock request detection circuit, 65 Near block down counter, 66: Exception control circuit, 71: Control store, 72 Near address register, 78: Adder circuit, 74: Branch control circuit, 75: Command register, 76: 7 Rip 70 block. (a) (b) Figure 3 Figure 4 Cause 5

Claims (1)

[Claims] configured with a plurality of processors and a common storage device,
In a multiprocessor system that performs lock/unlock exclusive control, a test and lock request means performs a test and lock request, and the test and lock request is successful. lock success detection means for detecting a lock success; unlock request means for making an unlock request; unlock request detection means for detecting an unlock request; A multiprocessor characterized by: means for holding information for identifying whether or not there is at least one thing locked by the processor when the unlock request detecting means detects an unlock request. system.