JPS6077447A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS6077447A
JPS6077447A JP58186157A JP18615783A JPS6077447A JP S6077447 A JPS6077447 A JP S6077447A JP 58186157 A JP58186157 A JP 58186157A JP 18615783 A JP18615783 A JP 18615783A JP S6077447 A JPS6077447 A JP S6077447A
Authority
JP
Japan
Prior art keywords
film
resin film
ray shielding
thickness
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP58186157A
Other languages
Japanese (ja)
Inventor
Minoru Inoue
実 井上
Yasutaka Ban
伴　保隆
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP58186157A priority Critical patent/JPS6077447A/en
Publication of JPS6077447A publication Critical patent/JPS6077447A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W42/00—Arrangements for protection of devices
    • H10W42/20—Arrangements for protection of devices protecting against electromagnetic or particle radiation, e.g. light, X-rays, gamma-rays or electrons
    • H10W42/25—Arrangements for protection of devices protecting against electromagnetic or particle radiation, e.g. light, X-rays, gamma-rays or electrons against alpha rays, e.g. for outer space applications
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
    • H10W70/68—Shapes or dispositions thereof
    • H10W70/682—Shapes or dispositions thereof comprising holes having chips therein
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/075—Connecting or disconnecting of bond wires
    • H10W72/07551—Connecting or disconnecting of bond wires characterised by changes in properties of the bond wires during the connecting
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/59—Bond pads specially adapted therefor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/851—Dispositions of multiple connectors or interconnections
    • H10W72/874—On different surfaces
    • H10W72/884—Die-attach connectors and bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/931—Shapes of bond pads
    • H10W72/932—Plan-view shape, i.e. in top view
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/931—Shapes of bond pads
    • H10W72/934—Cross-sectional shape, i.e. in side view
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/981—Auxiliary members, e.g. spacers
    • H10W72/983—Reinforcing structures, e.g. collars
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/734—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked insulating package substrate, interposer or RDL
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/754—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked insulating package substrate, interposer or RDL

Landscapes

  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Formation Of Insulating Films (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【発明の詳細な説明】 （ａｌ　発明の技術分野 本発明は半導体装置に係り、特に半導体装置に於けるα
線による障害を防止する構造に関する。DETAILED DESCRIPTION OF THE INVENTION (al) Technical Field of the Invention The present invention relates to a semiconductor device, and in particular to α in a semiconductor device.
It relates to a structure that prevents troubles caused by wires.

（ｂ）　技術の背景 高密度高集積化された半導体メモリ、特に容量に電荷を
保持することによって情報の記憶がなされるダイナミッ
ク型ランダムアクセスメモリ（Ｄ〜ＲＡＭ）等に於ては
、外囲気構成部材（パッケージ部材）や封止材料等に含
まれる微量の放射性元素から発生するα線によって記憶
情報が反転せしめられるいわゆるソフトエラー等が大き
な問題となっている。(b) Background of the technology High-density and highly integrated semiconductor memories, especially dynamic random access memories (D-RAM) that store information by holding charge in their capacitances, require an ambient air configuration. So-called soft errors, in which stored information is reversed by alpha rays generated from trace amounts of radioactive elements contained in components (package components), sealing materials, etc., have become a major problem.

ｔｅｌ　従来技術と問題点 そこで上記α線による障害を防止する一手段として、メ
モリ素子等が形成されている半導体基板の表面罠所望の
厚さを有するα線遮蔽用樹脂膜を形成し、この樹脂膜内
でα線をくい止めることによって素子の機能を保護する
方法が用いられている。そして従来該α線遮蔽用樹脂膜
には厚い皮膜の形成が比較的容易で、且つ耐熱性及び絶
縁性がすぐれたポリイミド膜単体成るいは高純度シリコ
ン、パラフィン等をフィラーに含んだポリイミド膜等が
主として用いられていた。しかしこれら従来のα線遮蔽
用樹脂膜に於ては、該樹脂膜を構成する物質中例於ける
α線の飛程（入射α粒子のエネルギーがｉになる膜厚）
が、ポリイミド：３５〔μｍ〕、シリコン＝３０〔μｍ
〕、パラフィン＝６０〔μｍ〕程度といずれも長いため
に、α線を充分に遮蔽するためにはその膜厚ｆｒ、４０
〜５０［μｍ）程度に著しく厚く形成する必要がめった
。そのため素子形成を完了した、即ちウェーハプロセス
を終った半導体基板上にスピンコード法を用いて該樹脂
膜を形成する際、スピンコードの際の回転数を落して１
回のコーティングで上記膜厚の樹脂膜を形成すると、塗
布むらが大きくα線の遮蔽効果が不充分になる場合がお
る、そこで均一な膜厚を得るためには、スピンコード及
び塗布膜のキュアーを複数回に分けて行う必要があり、
工程が非常に複雑例なっていた。tel PRIOR TECHNOLOGY AND PROBLEMS Therefore, as a means of preventing damage caused by the above-mentioned alpha rays, an alpha ray shielding resin film having a desired thickness is formed on the surface of a semiconductor substrate on which memory elements etc. are formed, and this resin film is A method is used to protect the functionality of the device by blocking alpha rays within the film. Conventionally, the α-ray shielding resin film is made of a single polyimide film, which is relatively easy to form a thick film, and has excellent heat resistance and insulation properties, or a polyimide film containing high-purity silicon, paraffin, etc. as a filler. was mainly used. However, in these conventional α-ray shielding resin films, the range of α-rays in the material constituting the resin film (film thickness at which the energy of incident α particles becomes i)
However, polyimide: 35 [μm], silicon = 30 [μm]
] and paraffin = about 60 [μm], so in order to sufficiently shield α rays, the film thickness fr should be 40 [μm].
It was often necessary to form the film extremely thick to about 50 [μm]. Therefore, when forming the resin film using the spin code method on a semiconductor substrate on which element formation has been completed, that is, the wafer process has been completed, the rotation speed during the spin code is reduced to 1.
If a resin film with the above thickness is formed by multiple coatings, the coating may be uneven and the alpha ray shielding effect may be insufficient. Therefore, in order to obtain a uniform film thickness, it is necessary to use a spin cord and cure the coated film. It is necessary to do this in multiple times,
The process was extremely complex.

ｔｄ）　発明の目的 本発明は上記問題点に鑑みなされたもので、その目的と
するところは一回のスピンコードで均一な厚さが得られ
るような薄い膜厚で遮蔽効果を充分に有するα線遮蔽用
樹脂膜を提供し、該半導体装置の製造工程を簡略化する
ことにある。td) Purpose of the Invention The present invention was devised in view of the above-mentioned problems, and its purpose is to provide α that has a sufficient shielding effect with a thin film that can obtain a uniform thickness with one spin code. An object of the present invention is to provide a line-shielding resin film and simplify the manufacturing process of the semiconductor device.

（ｅｌ　発明の構成 即ち本発明は半導体装置に於て、少なくとも機能素子が
形成されている領域の上部が、金属粒を含み且つ絶縁性
を有する樹脂膜で覆われてなることを特徴とする。(el) The structure of the invention, that is, the present invention is characterized in that, in a semiconductor device, at least the upper part of a region in which a functional element is formed is covered with a resin film containing metal grains and having an insulating property.

（ｆｌ　発明の実施例 本発明に於ては、下表に示したように金属材料がポリイ
ミドや従来フィラーとして用いられたバラフィンやシリ
コン等に比べて著しくα線の飛程が短かい点、及び高純
度に精隼１１されたこれら金属類に於てはそれ自体く含
まれるウラン（Ｕ）、トリウム（Ｔｈ）等の放射性元素
の量もポリイミドと同程度の１〜３　（ｐｐｂ）程度で
あることに着目し、これら金属の超微粉末（粒子の大き
さ数１００ＣＡ）程度）を、ポリイミド等の耐熱性及び
高絶縁性を有する樹脂中に、その絶縁性が損なわれない
範囲で出来るだけ多量の割合（４０〜６０（ｗｔ％〕程
度）でフィラーとして混入し、これによって該樹脂膜中
に於けるα線の飛程を縮小せしめ、薄い膜厚の該樹脂膜
によって充分なα線遮蔽効果を有せしめたものである。(fl Embodiments of the Invention In the present invention, as shown in the table below, the metal material has a significantly shorter range of alpha rays than polyimide, paraffin, silicon, etc. used as fillers in the past, and These metals refined to high purity11 contain radioactive elements such as uranium (U) and thorium (Th) at about 1 to 3 ppb (ppb), which is about the same as polyimide. Focusing on this, ultrafine powder of these metals (particle size of about 100 CA) is added to a heat-resistant and highly insulating resin such as polyimide in as much as possible without impairing its insulating properties. (approximately 40 to 60 (wt%)) as a filler, thereby reducing the range of alpha rays in the resin film, and the thin resin film has a sufficient alpha ray shielding effect. It has been made to have.

以下発明を実施例について、口金用いて説明す第１１メ
１は本発明の・一実施例に係る半導体チップを模式的に
示した上面図（イ）及びそのＡ−Ａ矢視断面＋ｄ（ロ）
である。図中１は半導体基板、２けダイナミ、りｒ、ｔ
ｏｓメモリ等が形成されている機能素子形成領域、３は
下層絶縁膜、層間絶ｐ、膜、カバー絶縁膜を含めた二酸
化シリコン（ＳｊＯｚ）、りん珪酸ガラス（ＰＳＧ）等
よりなる絶縁１１！ｉＥ、４けアルミニウム（Ａｚ）等
よりなるボンディング・パッド、５は例えばニッケル（
Ｎｉ　）等の超微粉末ｔ　６０　（ｗｔ％〕程度混合し
たポリイミドよりなる厚さ１５〔μｍ〕程度のα線遮蔽
用１ｌＩｙノ脂膜、６はワイヤポンディング用の開孔葡
示している。Embodiments of the present invention will be described below using a base. Eleventh image 1 is a top view (a) schematically showing a semiconductor chip according to an embodiment of the present invention, and its cross section taken along line A-A +d (ro). )
It is. In the figure, 1 is a semiconductor substrate, 2 is a dynamic, r, t
A functional element forming area 3 in which an OS memory etc. is formed is an insulation layer 11 made of silicon dioxide (SjOz), phosphosilicate glass (PSG), etc., including a lower layer insulation film, an interlayer insulation layer, a film, and a cover insulation film. iE, 4 bonding pads made of aluminum (Az), etc., 5, for example, nickel (Az), etc.
A 1lIy oil film for shielding α-rays with a thickness of about 15 [μm] is made of polyimide mixed with about 60 (wt%) of ultrafine powder such as Ni), and 6 indicates an opening for wire bonding.

本発明の構造に於ては、同図に示したように１半導体チ
ッゾの少なくとも機能素子が形成されている領域２の上
部が例えば上記のようにＮｉ超微粉末を多量に含んだポ
リイミドよりなるα線遮蔽用樹脂［５で覆われている。In the structure of the present invention, as shown in the figure, at least the upper part of the region 2 in which the functional elements of the semiconductor chip are formed is made of polyimide containing a large amount of ultrafine Ni powder as described above. Covered with α-ray shielding resin [5].

なお該α線遮蔽用樹脂膜５は、該樹脂膜中に含ませた金
属林料中のα諌飛程の１．５倍程度の厚さに形成する　
これによって従来と同程度のα線遮蔽効果が得られる。The α-ray shielding resin film 5 is formed to have a thickness approximately 1.5 times the α-ray range in the metal forest material contained in the resin film.
As a result, an α-ray shielding effect comparable to that of the conventional method can be obtained.

そして核α線遮蔽用樹脂膜５はボンディング争バッド４
の外側の領域には形成されなくてもよい。And the nuclear alpha ray shielding resin film 5 is the bonding competition bad 4.
It does not have to be formed in the area outside of.

第２図（イ）乃至（ハ）は上記実施例の構造を形成する
際の製造方法の一例を模式的例示した工程断面図である
、次にこれ等の図を参照し、その形成方法について説明
する。FIGS. 2(A) to 2(C) are process cross-sectional views schematically illustrating an example of the manufacturing method for forming the structure of the above embodiment.Next, referring to these figures, the formation method will be explained. explain.

第２図（イ）参照 通常の方法に従って、表面部にＤ−ＲＡＭ等の素子が形
成された機能素子形成領域２ｔ−有し、上面に形成され
たＳｉｎ、及びＰＳＧ等よりなる絶縁膜３の上面にボン
ディング・バッド４が表出されてなる複数のチップ領域
７を有する半導体基板１を形成する。なお図中８はダイ
シング・ラインを表わしている。Refer to FIG. 2(a). In accordance with the usual method, an insulating film 3 formed on the upper surface is formed of a functional element forming region 2t, in which elements such as D-RAM are formed, and is made of Sin, PSG, etc. A semiconductor substrate 1 having a plurality of chip regions 7 with bonding pads 4 exposed on the upper surface is formed. Note that 8 in the figure represents a dicing line.

第２図（ロ）参照 次いでポリアミドに対して例えば６０［：ｗｔ％〕程度
の割合で高純度Ｎ＋超微粉を混合しアセトン等しＬ の溶剤によって所望の粘度に希祿１粒子入りポリアミド
液を用い、例えば５００〜６００　［ｒ、　ｐ、ｎ＋）
程度の回転速度を有するスピンコードにより上記基板の
表面にα線遮蔽に必要な最終膜厚（ここでは１５（ｚｔ
ｍ））にキュアーによる減少分を加味した厚さの該ポリ
アミド膜を形成し、次いで貿素（Ｎ２）中で１５０〜２
５０〔℃〕程度の温度で所定の時間キュアーを行って、
該基板面全域上に高純度Ｎｉ超徽粉末ｉ６０〔Ｗｔ’％
〕程度の割合で含んだポリイミドよりなる厚さ１５〔μ
ｍ〕程度のα線遮蔽用樹脂膜５を形成する。Refer to Figure 2 (B). Next, mix high-purity N + ultrafine powder at a ratio of about 60 [wt%] to the polyamide, add acetone, etc., and adjust the polyamide solution containing 1 particle to the desired viscosity using a solvent such as acetone. For example, 500 to 600 [r, p, n+)
A spin cord having a rotational speed of about
m)) The polyamide film is formed to a thickness that takes into account the reduction due to curing, and then the polyamide film is heated to a thickness of 150 to 2
Curing is performed at a temperature of about 50 [℃] for a specified period of time,
High purity Ni powder i60 [Wt'%
] thickness of 15 [μ
m] of α-ray shielding resin film 5 is formed.

なお本発明に係るα線遮蔽用樹脂膜の厚さは１０〜１５
〔μｍ〕程度で充分であるので、該皮膜は１回のスピン
コードにより均一なル）、厚に形成することが可能であ
る。Note that the thickness of the α-ray shielding resin film according to the present invention is 10 to 15
Since a thickness of approximately [μm] is sufficient, the film can be formed to a uniform thickness by one spin cord.

第２図（ハ）参照 次いで図示しないレジスト膜をマスクにして酸素（０，
）プラズマ等による選択的なアッシング処理を行い、該
α線遮蔽用樹脂膜５にボンディング・バッド４及びダイ
シング・ライン８を個々に表出する開孔６及び９を形成
する。Refer to FIG. 2(c) Next, using a resist film (not shown) as a mask, oxygen (0,
) A selective ashing process using plasma or the like is performed to form openings 6 and 9 in the α-ray shielding resin film 5 to expose the bonding pads 4 and dicing lines 8 individually.

次いで図示しないが、前記ダイシング・ライン８に於て
該半導体基板を切断し、第１図に示した半導体チップを
形成する。Although not shown, the semiconductor substrate is then cut along the dicing line 8 to form the semiconductor chip shown in FIG.

第３図は本発明に係る半導体装置の封止完了状態の一例
を模式的に示した断面図で、図中１は半導体基板、２は
機能素子形成領域、４はボンディング・パッド、５は高
純度Ｎｉ超微粉末を含んだポリイミドよりなるα線遮蔽
用樹脂膜、１０ａ及び１０ｂはセラミ、り・パッケージ
、１１はチップ・ステージ、１２はチップ固定材料、１
３は内部リード、１４はボンディング・ワイヤ、１５は
セラミ、り・キャップ、１６は封止用ガラスヲ示してい
る。なお膣口に於ては絶縁膜は省略されている。FIG. 3 is a cross-sectional view schematically showing an example of a completed sealing state of a semiconductor device according to the present invention, in which 1 is a semiconductor substrate, 2 is a functional element formation region, 4 is a bonding pad, and 5 is a high α-ray shielding resin film made of polyimide containing ultrafine purity Ni powder, 10a and 10b are ceramic, resin packages, 11 are chip stages, 12 are chip fixing materials, 1
3 is an internal lead, 14 is a bonding wire, 15 is a ceramic cap, and 16 is a sealing glass. Note that the insulating film is omitted at the vaginal opening.

このような構造に於て、パッケージやキャップを構成し
ているセラミック材料、封止用ガラス、ボンディング・
ワイヤ等に含まれる微量の放射性物質からパッケージ内
部にα線が放出されるが、本発明に係る半導体チップに
於ては機能素子形成領域２の上部が前記α線遮蔽効果が
充分なポリイミド膜よりなるα線遮蔽用樹脂膜４で覆わ
れているので該機能素子形成領域２内に到達するα線は
殆んどなくなる。、従って該領域２に形成されているメ
モリ素子のソフトエラーは大幅に減少する１、なお本発
明に係るα線遮蔽用樹脂膜はエポキシ樹脂等を用いて形
成してもよい。又混入する金属粒として画表に示された
種類の金属はいずれも使用可能であり、画表以外でアル
ミニウム等も使用できる。In such a structure, the ceramic material that makes up the package and cap, the sealing glass, the bonding
α-rays are emitted into the package from trace amounts of radioactive substances contained in wires, etc., but in the semiconductor chip according to the present invention, the upper part of the functional element formation region 2 is made of a polyimide film that has a sufficient α-ray shielding effect. Since it is covered with the α-ray shielding resin film 4, almost no α-rays reach the functional element forming region 2. Therefore, the soft errors of the memory element formed in the region 2 are significantly reduced.1 The α-ray shielding resin film according to the present invention may be formed using an epoxy resin or the like. Furthermore, any of the metals shown in the diagram can be used as the mixed metal particles, and aluminum or the like other than those shown in the diagram can also be used.

（ｇｌ　発明の詳細 な説明したように本発明に係るα線遮蔽用樹脂膜に於て
は、薄い塗布膜厚で充分なα線遮蔽効果が得られる。(gl As described in detail about the invention, in the α-ray shielding resin film according to the present invention, a sufficient α-ray shielding effect can be obtained with a thin coating film thickness.

従って本発明によればα線遮蔽用樹脂膜の塗布及びキュ
アーエ税が１回ですむので、該α線遮蔽用樹脂膜を設け
るダイナミックメモリ等の半導体装置の製造工程が簡易
化される。Therefore, according to the present invention, the coating and curing process of the α-ray shielding resin film can be performed only once, thereby simplifying the manufacturing process of a semiconductor device such as a dynamic memory in which the α-ray shielding resin film is provided.

【図面の簡単な説明】[Brief explanation of drawings]

第１図は本発明の一実施例に係る半導体チップを模式的
ＶＣ示した上面図（イ）及びＡ＝Ａ矢視断面図（ロ）、
第２図（イ）乃至（ハ）は上記実施例の構造を形成する
際の製造方法の一例を模式的に示した工程断面図で、第
３図は本発明に係る半導体装置の封止完了状態の一例を
模式的に示した断面図である。 図に於て、ｌは半導体基板、２は機能素子形成領域、３
は絶縁膜、４はボンディング書パッド、５けα線遮蔽用
樹脂膜、６はワイヤボンディング用開孔を示す。 ％　１　図 第　２　図 （つ） ｊ２　ｉ　ブFIG. 1 is a top view schematically showing a VC of a semiconductor chip according to an embodiment of the present invention (A) and a cross-sectional view taken along the A=A arrow (B);
2(A) to 2(C) are process cross-sectional views schematically showing an example of the manufacturing method when forming the structure of the above embodiment, and FIG. 3 is a completed sealing of the semiconductor device according to the present invention. FIG. 3 is a cross-sectional view schematically showing an example of the state. In the figure, l is the semiconductor substrate, 2 is the functional element formation region, and 3 is the semiconductor substrate.
Reference numeral 4 indicates an insulating film, 4 indicates a bonding pad, 5-digit α-ray shielding resin film, and 6 indicates an opening for wire bonding. % 1 Figure 2 (tsu) j2 i b

Claims (1)

【特許請求の範囲】[Claims] 少なくとも機能素子が形成されている領域の上部が、金
属粒子を含み且つ絶縁性を有する樹脂膜で榎われてなる
ことを特徴とする半導体装置。1. A semiconductor device characterized in that at least an upper part of a region where a functional element is formed is covered with an insulating resin film containing metal particles.
JP58186157A 1983-10-05 1983-10-05 Semiconductor device Pending JPS6077447A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58186157A JPS6077447A (en) 1983-10-05 1983-10-05 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58186157A JPS6077447A (en) 1983-10-05 1983-10-05 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS6077447A true JPS6077447A (en) 1985-05-02

Family

ID=16183375

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58186157A Pending JPS6077447A (en) 1983-10-05 1983-10-05 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS6077447A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0671768A3 (en) * 1994-02-14 1997-08-20 Texas Instruments Inc Improvements in or relating to electrodes for LSI.
JP2008272357A (en) * 2007-05-07 2008-11-13 Hoya Corp Endoscope support device
JP2009017973A (en) * 2007-07-10 2009-01-29 Okamura Corp Cart with tray

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5790966A (en) * 1980-11-26 1982-06-05 Nec Corp Semiconductor device

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5790966A (en) * 1980-11-26 1982-06-05 Nec Corp Semiconductor device

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0671768A3 (en) * 1994-02-14 1997-08-20 Texas Instruments Inc Improvements in or relating to electrodes for LSI.
JP2008272357A (en) * 2007-05-07 2008-11-13 Hoya Corp Endoscope support device
JP2009017973A (en) * 2007-07-10 2009-01-29 Okamura Corp Cart with tray

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