JPS6079391A - Display controller - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a display control device, particularly a display device that displays images such as characters and figures by rask scanning on a refresh gamma display device such as a cathode ray tube (CRT). This relates to a control device.

[Such a display control device usually has a video memory, from which pixel data is taken out and output as a video signal to the display device. Such a display control device uses video memory (
, VRAM), VRAM address circuits, and display device synchronization generation circuits are available as general-purpose LSIs.

In a rask scanning type display control device, data is stored in a video memory in units of pixels. This method has the advantage of being able to display graphics in addition to characters, compared to the method of storing display data in the middle of characters, but has the disadvantage of being slow at rewriting pixel data. In other words, since the amount of data that constitutes one screen's worth of pixels is large, it takes a relatively long time to rewrite them. This is especially noticeable when scrolling the screen. For example, some commercially available LSIs require nearly one second to scroll, reducing the operability of the display device.

In order to shorten this scrolling time, a raster pointer is provided in a certain area in memory that specifies the start address of pixel data on the VRAM for each horizontal scanning line that makes up one screen, and when scrolling, Rather than updating the entire pixel memory, the contents of the raster pointer,
That is, there is a method in which only the first address of each horizontal scanning line is rewritten. Since this method cannot utilize the aforementioned general-purpose LSI, the CRT control function had to be realized using random wiring logic. Since this control function is relatively complicated, the control circuit has a complicated configuration and the display control device is also large-sized.

■--The present invention eliminates the shortcomings of the prior art, takes advantage of the advantages of the raster scanning method that can display not only characters but also graphics, and provides display control that can update the screen at high speed with a simple device configuration. The purpose is to provide equipment.

The configuration of the present invention will be described below based on one embodiment.

Referring to FIG. 1, in an embodiment of a display control device according to the present invention, a processing device such as a microprocessor, for example,
A display control device is connected between O and a display device 12 such as a CRT, and this display control device is composed of a video memory circuit 100 and a sequencer circuit 200. The display device 12 displays images such as characters and figures by raster scanning.

The video memory circuit lOO includes a memory that stores pixel data forming a screen by raster scanning, as described below.
It is connected to the processing device IO by an address north 14 and a data bus 16, and to the display device 12 by a connection line 18 for transferring a video signal VIDEO, a connection line 20 for transferring a synchronization control signal, etc. ing. The sequencer circuit 200 is the video memory circuit 10
This is a control circuit that controls the operation of 0, and as will be described later, its control function is realized by timing control logic stored in ROM. This is connected to the video memory circuit 100 by a multi-wire control line 22, and to the display device 12 by a connection 1i for transferring synchronization control signals, etc.
28, etc. Furthermore, an external video clock signal VCIJ is input to the sequencer circuit 200 via a control line 24 . Note that other connection lines and the like that are not directly related to the understanding of the present invention are omitted from the drawing to avoid complicating the drawing.

Referring to FIG. 2, the same components as in FIG.
An address bus 14 extending from address latch 32 from address input 104 of RAM 102 is connected to address input 104 of RAM 102, which also includes a game) lOf! , 10B and 180 outputs are also connected. A data bus 16 extending from CPU 30 through bidirectional data buffer 34 is connected to data input 164 of RAM 10.2 via gate +14, to which also the output of gate 112 is connected. These address launches 32, data buffers 34, and gates 108, 108, 112
, 114 and 190, etc. are energized and deenergized by control outputs 22 and 2B of sequencer circuit 200.

Taking gates 10B and 10B as an example, it can be seen that they are operated by signals ARM and AR, respectively.

As shown in FIG. 4, the RAM 102 is mainly used as a video memory 116, in which pixel data for one screen to be displayed on the display device 12 in a raster scanning manner is stored in storage locations corresponding to each horizontal scanning line. be done. It is also used as an area for a raster pointer 118 and a raster counter 120, as will be described later. Raster pointer 1 like this
By using the same storage area of the memory chip as the video memory ttS for the management memory map such as 18 and raster counter 120, the configuration of the access circuit therefor is simplified. RAM 102 may also be used as a work area for CPU 10.

The data output 122 of the RAM 102 is the input 124 of the gate 112 and the input 12 of the shift register (R1) 12fl.
8. and the human power 132 of the parallel-to-serial conversion circuit 130, respectively. The parallel-to-serial conversion circuit 130 responds to the control output signal VL port of the sequencer circuit 200 to
This is a shift register circuit that loads the data of No. 2 and outputs it to the output 134 as a serial signal and a video signal in response to the same VCLK.

The shift register 12G has the data of the input 1211 loaded into the control output signal RL1 of the sequencer circuit 200, and its output 13B is the input 14G of the counter (R2) 138.

and a video address counter (VAC) 142 human power +44. Video address counter 1
42 is an address counter of the RAM 102, and its output 14B is connected to the gate 108. Data loading to the video address counter 142 is performed by the control output signal RTH of the sequencer circuit 200, data loading to the counter 138 is performed by the control output signal RL2 of the sequencer circuit 200, and counting is performed by the same RCυ. The output 148 of counter 138 is the input 152 . of gate 150 . One input 15 of the comparison circuit 154
B and input 158 of gate 108, respectively. The gate 150 is operated by the control output signal RTM of the sequencer circuit 200, and its output 180 is connected to the data input 1[14 of the RAM+02 together with the output 182 of the gate +14.

Comparison circuit 154 compares the count value of counter 138 with a set value, and when the two match, drives flip-flops (FF) 1813 and 188 at its output.

The reference data for comparison is the other input 174 of the comparison circuit 154.
is input. This may be fixed, semi-fixed with a manual switch, or settable from the CPU 30. As will be described later, in this embodiment, the video gate signal VGT is in the pixel period 19.
The reference data is set to be at a high level from 7 to 838 (Figure 8).0 inputs 158 and 1
74, a vertical synchronizing signal VSY and a video gate signal VGT are formed. Vertical synchronization signal VSY is supplied to display device 12 via connection line 20. Video gate signal VGT is the other input 17 of ^NN low-170
The output 18 of the AND gate 170 is supplied to the display device fi 12 as a valid video signal VIDEO.

In this embodiment, the sequencer circuit 200 that generates timing control signals for controlling each part of the video memory circuit 200 includes a counter 202° ROM 204 as shown in FIG.
．． It is composed of a latch 20θ, a decoder 208, and the like.

This embodiment is applied to an example in which the display screen of one display device-12 is composed of 4QO horizontal scanning lines, and one horizontal scanning line ('1)1) is composed of 640 pixels. Of course, the present invention is not limited to this, and it goes without saying that it can be advantageously applied to any other value.
The OM 204 1) has storage locations corresponding to one period, but 1) has 838 storage locations or effective addresses, which is the number of effective pixels in one period, 840, plus 187 pixel periods corresponding to the horizontal retrace period. . Therefore counter 20
2, in response to the video dot clock CLK, this 8
This counter increments by sequentially specifying 38 addresses.

Also, the effective horizontal scanning line is 400 lines, and 424H, which is the vertical blanking period of 24H, is one vertical scanning period (
tV). Therefore, as shown in FIG. 4, the video memory 1113 of the video memory circuit 100 occupies a storage area equivalent to 424H, and the rask pointer +
18, I■ corresponds to two storage locations.

Returning to the sequencer circuit 200, the latch 206 is a ROM
The output data of 204 is accumulated and held. A part of the held data is output to the video memory circuit 100 and the CRT display device 1112 through connection lines 22 and 2B, respectively, and the other part is output to the decoder 208. Decoder 2
0B expands the output data of latch 206 and outputs it as various timing control signals to video memory circuit +00 and CR7 display device 12, also through connection lines 22 and 2B, respectively. That is, many of the timing control signals described with respect to FIG.
The data load signal RL2 and the like are connected to the connection lines 22 and 26.
is output from.

The counter 202 increments in response to the clock CLK, and R
The addresses of OM and 204 are specified sequentially from 0 to 837 cyclically. That is, the IH period is cyclically advanced. In the ROM 204, various timing control signals to be output from the connection lines 22 and 26 corresponding to each pixel period included in the IH period are stored in the form of original data at corresponding addresses. Therefore, by sequentially specifying each address, the various timing control signals described above are output to the connection lines 22 and 2B at appropriate timings, and each part of the video memory circuit 100 and the display device 12 operate in accordance with these signals. It turns out. For example, the vertical synchronization signal H9Y is formed at the timing shown in FIG.
In this embodiment, the horizontal blanking period is the pixel period 837 to 54
It shows that it is over. Some of these timing control signals are also used to control each circuit of the CPU 30. These timing conditions can be easily changed by rewriting the storage contents of the ROM 204 (or replacing the ROM) according to the specifications of the display device 12 used.

The 838 pixel periods in the IH period described above are divided into cycles each having 16 pixel periods as a unit.Therefore, as shown in FIG. 5, the IH period consists of 53 cycles. Among them, the 11th to 50th cycles are used to update the display screen, and the 51st cycle and the 5th cycle are used to update the display screen.
2 cycles are used to update the VAC 142, and the remaining Oth cycle to 1st O cycle are used for updating the VAC 142, for example.
(direct memory access) control, input/output control of floppy disks, printers, etc., and external control such as CPU control. Further, as will be described later, a part of the screen update period is also used for control by the CPU 30, and in that case, the sequencer circuit 200. and idle circuit elements such as registers and counters of video memory circuit 100 may be used for CPo 30 task processing.

Referring to the functional diagram of FIG. 4 and the time chart of FIG.
The cycle is performed as follows. Note that in both figures, numbers in parentheses indicate corresponding operations. Also,
The numbers at the top of FIG. 6 indicate the pixel period, and it can be seen from this that one cycle consists of 18 pixel periods as described above.

In this mode, CCY and CBY are in the state shown in FIG. 6, and first, the address of raster counter +20 in RAM 102 is designated by timing (address bus) control signal ARC (1). This is a game) 1!110
This is based on fixed information 192 as human input information and information 1flll from the sequencer. This is done by reading out the storage location in RAM 102 specified by the address using memory timing signals RAS and CAS. Next, data cn is transferred from the raster counter 120 to the shift register 12B by the timing control signal RLI.
(2). This data cn is loaded into the counter 138 with the next timing control signal RL2 (3).

The data cn loaded into the counter 138 is transferred to the gate 108 by the timing (address bus) control signal AR.
is output to the address bus 14 via the address bus 14. This is R.A.
It is used for accessing RAM 102 as the address of raster pointer 118 in M 102 (4). The addressed content an of raster pointer 118 is then loaded into shift register 12B by timing control signal RLI (5).

This data an is then loaded into the VAC 142 by the timing control signal RTH (6).

By the way, the content cn of the counter 138 is incremented by 2 by the two timing control signals RCU, and becomes cn+2 (7). The reason for incrementing by 2 here is that IH corresponds to the two storage locations of the raster pointer 118 in RAM +02 as described above. ,
In the comparison circuit 154, the contents of the counter 138 cn+2
A comparison is made between the set standard data and the set standard data (8). As a result, the vertical synchronizing signal VSY and the valid type [video gate signal VGT that defines the self-scanning period] are applied to the flip-flop 1.
811 and 18B at corresponding timings. The video gate signal VGT indicates that 400 rasks from 24 to 424 of the raster address counter are an effective video period. This depends on the reference data set in the comparison circuit 154.

At the same timing, the timing control signal ARC activates the address launch 32, thereby specifying the address of the same raster counter 120 in the RAM 102 (9). Then, the gate 15o is opened by the timing (data bus) control signal DR, and the contents cn+2 of the counter 138 are written to the designated address of the RAM 102, that is, the raster counter +20. This is the memory timing signals RAS and CAS
, and the write control signal WT.

The content cn+2 of the counter 138 is reset to O at full count, that is, 424x2 in this embodiment.

At this time, the 1v period has passed.

Next, the operation of accessing pixel data stored in the video memory 11B and outputting it to the display device 12 as a VIDEO signal will be described with reference to time chart 1 in FIG. This occurs in each of the 11th through 5° cycles shown in FIG. As shown in Figure 7,
In the operation mode, the 9th pixel period from O is allocated to control by the CPU 30, such as floppy disk control, and the remaining 10th to 15th pixel periods are allocated to updating the display screen when the mode CCY becomes low level.

First, the contents an of the VAC 142 are outputted to the address bus as an address signal of RAM +02 by the timing (address bus) control signal ARM (11).

Therefore, the contents of the storage location an of the video memory 11B designated by this address, that is, the pixel data of the pixel in question, are read out by the memory timing signals RAS and GAS, and loaded into the parallel-to-serial conversion circuit 130 by the timing control signal VLD ( 12).

The pixel data loaded into the parallel-to-serial conversion circuit 130 is shifted at a pixel signal speed in response to the shift clock VCLK, and is sequentially output as a serial video signal. This is toN
(O game) At 170, the logical AND with the video gate signal VGT indicating the effective horizontal period is performed, and the V I for 16 pixels is calculated.
The signals are sequentially output to the display device 12 as DEO signals (1
3). On the other hand, VAC142 is the timing control signal RMU
is incremented by 1 to prepare for access in the next cycle, that is, access to the next 16 pixels in that scan line.

According to the present invention, timing control in the display control device is achieved by cyclically reading out the ROM storing timing control data for each horizontal scan. Therefore, the display control device according to the present invention has the following features:
It effectively utilizes the advantages of the raster scanning method, which has a simple device configuration, can update the screen at high speed, and can display not only characters but also graphics.

More specifically, not only the configuration of the sequencer is simplified, but also the configuration of the related control circuit of the video memory (VRAM). Conventionally, control circuits for each of many types of functions were constructed using wired logic, but according to the present invention, the same logic circuits such as registers and counters can be used redundantly for many types of functions. , because this can be achieved. This effect is large in practice.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of a display control device according to the present invention, FIG. 2 is a block diagram showing an example of the configuration of a video memory circuit in the embodiment shown in FIG. 1, and FIG. 3 is a block diagram showing the first factor. A block diagram showing an example of the configuration of the sequencer circuit in the embodiment, ft54 is a functional diagram for explaining the operation of the video memory circuit shown in wS2, and FIG. 5 is an explanation for explaining the overall operation in the l horizontal scanning period. Figure 6 is a timing diagram for explaining the memory address setting operation in the video memory circuit, Figure 7 is a timing diagram for explaining the video signal output operation in the video memory circuit, and Figure 8 is for the sequencer. FIG. 3 is a timing diagram showing a horizontal synchronization signal and a video gate signal formed in the circuit and the video memory circuit, respectively. --) Treasure 12゜11 Display device 100,...Video memory circuit 102...RAM 1ts...Video memory +18. ,, Raster pointer 120, , Raster counter 126, , Shift register 130, , Parallel-serial conversion circuit 138, , Counter 142, , Video address counter 154, , Comparison circuit 18E1.188. Blip-flop 200, Sequencer circuit 202, Counter 204, ROM 208, Latch Patent applicant Ricoh Co., Ltd.

Claims (1)

[Scope of Claims] The display device includes a first memory having a pixel data storage area for temporarily storing pixel data constituting an image, and an address control circuit for addressing the first memory. In the display control device for visually displaying a line table, the Jζ control device includes a second memory storing control data for controlling timing in the horizontal scanning period of the rask scan, and a second memory in synchronization with the horizontal scanning. a timing control circuit that cyclically reads control data from the first memory and forms a timing control signal for displaying an image, the address control circuit responding to the timing control signal and accumulating pixel data in the first memory. A display control device characterized in that an address of an area is updated for each horizontal scan, thereby reading pixel data from the pixel data storage area.