JPS6081981A - Solid-state image pickup device - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

TECHNICAL FIELD The present invention relates to solid-state imaging devices, and particularly to improvements in signal processing circuits thereof.

BACKGROUND ART A CCD type solid-state imaging device having a horizontal charge-coupled device and a MOS type solid-state imaging device (abbreviated as MOS sensor) having a horizontal signal line (abbreviated as HSL) are known. The biggest problem with these solid-state imaging devices is noise reduction. In particular, many prior art techniques have been proposed because the horizontal scanning noise of a MOS sensor and its dispersion extremely reduce the signal-to-noise ratio. In MOS area sensors, a typical prior art that has been put into practical use is a noise integration method. This is done by integrating the signal voltage over one pixel period.
This cancels horizontal scanning noise, which is an AC voltage.

JP-A-56-51166 discharges a capacitor using a discharge circuit that converts a signal voltage into a current, and then charges (resets) the capacitor via a clock-operated MOST.
Disclose what you will do. Japanese Patent Laid-Open No. 56-51167 discloses charging (resetting) the capacitor via a rectifying element after the above-mentioned discharge. The charging operation is then performed by applying a clock voltage to the other end of the capacitor.

Furthermore, Japanese Patent Laid-Open No. 56-51167 discloses the use of a bipolar transistor to which a DC voltage is applied to the base instead of the above-mentioned rectifying element. JP-A No. 58-77385 discloses that a color separation operation is performed by arranging (in parallel) a plurality of MOSTs disclosed in JP-A No. 56-51166.

DISCLOSURE OF THE INVENTION Although the above-mentioned prior art reduces horizontal scanning noise, many problems still remain. The first problem is to intermittently charge (reset) the capacitor and read out the signal voltage at the same time (this operation is described below as
This is abbreviated as "reset operation". ), in an embodiment using a MOST, a MOSIC is required in addition to the bipolar LSI, and the above-mentioned MOST clock voltage and its fluctuations are mixed into the output signal voltage. Furthermore, M.O.
Noise generated by the ST and variations in channel resistance of the MOST due to variations in the source or drain voltage of the MOST are also major problems. A second problem is that in embodiments in which the reset operation is performed by clocking one end of the integrating capacitor, fluctuations in the clock voltage become a very large noise source. In order to reverse bias the emitter of the bipolar transistor to which a DC voltage is applied to the A terminal or base of the rectifying element during the period when no reset operation is performed, the above clock voltage becomes considerably large. This is because the above-mentioned A terminal or emitter has a considerably large parasitic junction capacitance.

The third problem is that the output capacitance of the MOS area sensor using the conventional noise integration method is large.

This is because a well-known source follower MOS amplifier is built in on the same chip as the MOS area sensor, and when the voltage of the horizontal signal line is amplified by this amplifier and outputted, the linearity of the amplifier is poor, so a noise integration circuit is used. This is because the horizontal scanning noise cannot be canceled out. As a result, in conventional technology, the horizontal signal line needs to be connected to a sense amplifier fabricated on a separate chip with high linearity via a large coupling capacitor. Considering that the horizontal scanning noise voltage is much larger than the signal voltage, it will be understood that the output voltage needs to have good linearity up to the noise integration circuit. The linearity is improved by loading the depletion type MOST in which the built-in source follower amplifier has its gate and source connected, but it is not perfect. The source follower MOST and the load MOST generate relatively large noise, especially in the low frequency region. As a result of the above, in the prior art, a sense amplifier fabricated on a separate chip has a small signal voltage and large thermal noise due to the large input capacitance (vertical signal line capacitance + horizontal signal line capacitance + parasitic capacitance of the conductor). It will be understood to have.

The present invention has been made to improve the above-mentioned drawbacks of MOS area sensors. A part of the present invention can also be applied to a CCD area sensor. An object of the present invention is to improve the SN ratio of a solid-state imaging device or a MOS solid-state imaging device. To achieve the above object, this specification discloses three independent inventions. These are listed together because they have a very strong interrelationship and produce great synergistic effects when implemented together. The features and advantages of each independent invention are disclosed below.

Independent invention 1. (Claims 1 to 5) In a MOS area sensor having a noise integration circuit, the second end of the integration capacitor is connected to a DC power supply, and
The first end thereof is connected to a discharging circuit, and further connected to a charging circuit via a rectifying element.

The first end of the rectifying element connected to the first end of the charging circuit
The "reset operation" is controlled by controlling the potential at the end. In an embodiment in which the signal voltage is linearly amplified,
The first end of the rectifying element and the high-level power source are connected through a resistor. In one simple embodiment, the first end of the rectifying element is connected to a clock power supply via a resistor or rectifying element. In one preferred embodiment, a first end of the rectifying element is connected to a lower power supply through a transistor and a resistor to the base of which a clock voltage is applied. In the most preferred embodiment, the first end of the rectifying element is connected to a lower power source through a resistor and a transistor having a DC voltage applied to its base. and,
The emitter potential of the above transistor is controlled. It is equivalent to change the resistor to another non-linear element. In one embodiment for controlling the emitter potential, the emitter of a second transistor is connected to the emitter described above, and a clock voltage is applied to the base of the second transistor. In another embodiment, a clock voltage is applied to the emitter via a second rectifying element. In this way, the rectifying element (
The potential at the first end of 1) is not affected by clock voltage fluctuations. Details of the horizontal scanning noise canceling operation of the integrating circuit are the same as those of the prior art described above, so please refer to them. In a preferred embodiment, the rectifying element is a transistor connecting the base and collector. In this way, the rectification characteristics are improved.

Independent invention 2. (Claim 6) In a MOS area sensor, especially in a MOS area sensor that uses an integral method, by incorporating a source follower amplifier, the S/N ratio of the signal voltage of the horizontal signal line is improved, but the linearity is deteriorated. . The present invention is characterized in that a MOS area sensor incorporates an NPN bipolar output transistor whose collector is the substrate. It is preferable that the P-type base is made together with the P-type well of the image sensor. The horizontal signal line is connected to the base of this emitter follower amplifier. Emitter follower transistors have low noise and the emitter voltage follows the base potential well.

Independent invention 3. (Claims 7 and 8) In the MOS type or CCD type area sensor, the load element of the built-in output amplifier is made on a separate chip from the area sensor. In this way, the resistor or constant current load circuit which is the load element of the output amplifier described above can be accurately manufactured without increasing the number of steps for the area sensor. MOST load elements built into conventional area sensors had high noise and poor linearity. In a particularly preferred embodiment, by employing a constant current load, the source follower or emitter follower transistor built into the area sensor produces an output signal voltage with good linearity.

Other features and advantages of the invention are illustrated by the following examples.

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a block diagram of a conventional noise-integrating MOS area sensor. Specific examples of the noise integration circuit 8 are disclosed in FIGS. 2 to 4. FIG. 5 is an equivalent circuit diagram showing one embodiment of the noise integrating circuit of the present invention. 13 is a low power supply (for example, 0V), and 14 is a high power supply (for example, +
12V). When the signal voltage Vi is applied to the base of the transistor 16, the discharge current i1 becomes (Vi-VBE
)/R15. During one pixel period, the first
The end 17A integrates the current i1.

At the end of one pixel period, the potential V17A of the node 17A decreases from the reset potential VR by VDC+VAC. V
DC is the potential of the node 17A when the signal voltage component of the input voltage Vi is 0, and VAC is the integrated signal voltage component. AC noise voltages are canceled by integration. 1
At the end of the pixel period, node 17A is charged via rectifying element 18 and via resistor 19. The charging current i2 becomes (V14-V17A-VBE')/R19. Therefore, during this charging (resetting) period, the output terminal 20 receives i.
A voltage of 2×R19 is generated, and a change in this voltage V20 becomes a signal voltage. The discharge circuit 26 is composed of a transistor 16 and a resistor 15, and the charging circuit 25 is composed of a resistor 19 that connects the node 20 and the power source 14, a transistor 21 that connects the node 20 and the power source 13, and an emitter resistor 22. Ru. A rectifying element 23 is further added to connect the emitter of the transistor 21 and the clock power source. If, 2
Assuming that the VBEs of 1 and 23 are equal, if the clock voltage is greater than the DC voltage applied to the base of transistor 21, i3 is immediately cut off, and i4 = (φ - VBE) ÷ R
22 flows. When i3 becomes 0, the capacitor 17 is rapidly charged by the resistor 19 through the rectifying element 18.

At the beginning of one pixel period, the clock voltage becomes smaller than the DC voltage VDC applied to the base of 21, and as a result, i3
flows, and i4 is immediately cut off. i3 is (VDC-VBE
)÷R22, and the potential V20 of node 20 is V14-(
VDC-VBE)÷R22×R19, which is sufficiently smaller than the potential at node 17A. As a result, i2 is suddenly cut off. Pure discharge period (non-reset period) when i2 is briefly cut off
Although the potential at node 17A decreases, if current i3 or resistor 19 is set so that the potential at node 20 becomes smaller, i2 does not flow during the non-reset period. FIG. 6 shows a configuration in which a transistor 24 is connected in place of the rectifying element 23 in FIG. its collector is connected to a power supply 14;
A clock is applied to its base. In this way, the clock current can be reduced. 5 and 6, other parts may be added as long as the basic operation of the present invention is not impaired. FIG. 7 is a cross-sectional view showing the output transistor of the present invention. A P-type well 28 and a base 30 are formed on the surface of the N- substrate 29, and an N+
Areas 27A, 3A, and 31 are created. 27 is a vertical signal line, and 1 is an N-channel horizontal scanning transistor. 31 is an emitter of an emitter follower transistor whose collector is a substrate.

FIG. 8 is an equivalent circuit diagram of an emitter follower output amplifier using the emitter follower transistor of FIG. 7. The power supply 13 of the horizontal signal line 3 is connected through a resistor 4 . The horizontal signal line 3 is then connected to the base of the emitter follower transistor. The emitter is connected by an output line 10 to one end of a constant current load circuit 32 of another chip. The constant current load circuit is composed of a transistor 11 to the base of which a DC voltage is applied, and an emitter resistor 12.

In FIGS. 5 to 8, it is preferable that transistors other than the rectifying elements operate in saturation. In one embodiment of FIG. 5, C
17 is 40PF, R19 is 150Ω, R22 is 100Ω
It is.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a MOS area sensor having a conventional noise integration circuit 8. 2, 3, and 4 are equivalent circuit diagrams of the conventional noise integration circuit 8. 5 and 6 are equivalent circuit diagrams of the noise integrating circuit of the present invention. FIG. 7 is a sectional view showing one embodiment of the present invention. FIG. 8 is a block diagram showing another embodiment of the present invention. Patent applicant Shoichi Tanaka

Claims (8)

[Claims] (1). The above-mentioned noise removal circuit includes a horizontal signal line, a resistor that connects the horizontal signal line and a DC power supply, and a noise removal circuit that integrates AC noise included in the signal voltage.
It includes a discharging circuit controlled by a signal voltage, a capacitor, a rectifying element, and a charging circuit, the first end of the capacitor being connected to the first end of the discharging circuit and the first end of the rectifying element, A solid-state imaging device, the second end of which is connected to the first end of a charging circuit, wherein the potential of the first end of the charging circuit is controlled to intermittently charge the capacitor. (2). The second end of the above rectifying element is connected to the collector of the bipolar transistor, a DC voltage is applied to its base, and its emitter is connected to a DC power supply via a resistor to control the emitter potential. The solid-state imaging device according to item 1, characterized in that: (3). The emitter of the above bipolar transistor is electrically connected to the emitter of a second bipolar transistor, and by applying a clock voltage to the base of the second bipolar transistor, the above bipolar transistor (first) 3. The solid-state imaging device according to claim 2, wherein the solid-state imaging device controls conduction of the solid-state imaging device. (4). 3. The solid-state imaging device according to claim 2, wherein the emitter of the bipolar transistor is connected to a clock power source via a rectifier. (5). 2. The solid-state imaging device according to claim 1, wherein the rectifying element is a bipolar transistor whose base and collector are connected. (6). In a solid-state imaging device that includes a horizontal signal line and a resistor that connects the horizontal signal line and a reference power source, the horizontal signal line is N
A solid-state imaging device connected to the base of a PN bipolar transistor, the collector of which is a substrate. (7). A solid-state imaging device, wherein a solid-state imaging device incorporating a signal output transistor and a load element of the signal output transistor are formed on different chips. (8). 8. The solid-state imaging device according to item 7, wherein the load element is a constant current load.