JPS6083154A - Data memory - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a data storage device that can write and read data from both row and column directions at high speed.

Conventional chestnut structure and its problems As a method to write and read data in N bits parallel from column direction to N memories that can operate independently, all data is written in row direction and column direction. Each block is divided into N bits each, and a block composed of NXN bits is a processing unit, and N memories that can operate in parallel so that data in the same row and column in the block are not allocated to the same memory. A method has been devised to allocate and memorize the information.

For example, as a method of allocating and storing data in the same row and column in a block in different memories,
32, the first row (i-1~
This is a method of cyclically shifting the data of 32) by one bit and allocating and storing the data of the first row in addresses 32k(, +i-1) of each memory.
This is a diagram showing 2x32 bit data. Figure 2 shows the memory m1 to m when the data in Figure 1 is allocated in the above method.
32 is a diagram showing data stored in 32. FIG.

Figure 3 is a diagram showing the addresses given to the memory when writing and reading in the column direction when data is allocated to the valley memory as shown in Figure 2.As is clear from Figure 3, when data is allocated to the valley memory, For reading, the value obtained by adding the address given to the memory by 1 (when the address of memory mjld32ko+i is given, the memory mj has 32)+mod32(i+
Here)) will be given. Unfortunately, it is necessary to provide each memory with an address that has been subjected to address conversion, and this has the drawback that the circuit scale required for memory address conversion increases in proportion to N.

However, as N becomes larger, it becomes necessary to construct a cyclic shift register that can operate at high speed, and there is a drawback that heat generation occurs due to the use of elements that can operate at high speed.

OBJECT OF THE INVENTION The object of the present invention is to have N=2 memories that can operate independently, and to store data from the row direction and from the column direction.
Data in a data storage device that can write and read bits in parallel, suppressing the increase in circuit scale required for address conversion processing for memory, and reducing the part that must be processed at high speed when rearranging data. It is to provide a storage device.

Structure of the Invention In order to achieve the above object, the present invention provides 2n14-n
A block consisting of 2×2n1+n2 bits of data is divided into two bits in each row and column direction.
, 2" x 2" bit data constitutes 2 x 2 units as one unit, and for the input data of 2n1 + n2 binoto in the row direction (or column direction) within the block, the 2n 2 to which the input data belongs cyclically shifting a predetermined amount in bit units corresponding to the position occupied by the 2-bit data in each unit, and a predetermined amount corresponding to the position occupied in the 2n2 valley units to which the input data belongs within the block. The data is rearranged by cyclically shifting the data in units of 2 bits, and two memos that can operate independently are created.
m, 21...+ m,, i11+12 address input 'O+a1+...+anl-1', address input for each memory m2H,...+ anl-1 is common. Address value u1 is input, each memory m2n10. +2 address input is shared and address value u2 is input.

......, each memory m2n11, +2n1 (o≦1
≦2-1) address input is common and the address value u2
Wiring so that n1 is input, address input bO, b1
．． .......

Regarding the n2 pieces of bn2-+, C, the address input of each memory mj is made common and the address value v1 is input, the address input of each memory m2n1+ is made common and the address value v2 is input,..., valley Memory mz”N (
2n2-+)+F(1≦K≦2n1), and wire it so that the address value vy is input, and the address value u) ((1≦X≦2n1) in the row direction in the Iri block. When writing/reading data from (column direction), set to the same value according to the data position; when writing/reading data from column direction (row direction), set to individual values according to the data position. , address value Vy (1≦
y≦2n2) is set to the same value according to the data position when writing/reading data from the row direction (column direction) within the block, and is set to the same value according to the data position when writing/reading data from the column direction (row direction). Set it to an individual value depending on the position.

DESCRIPTION OF EMBODIMENTS Hereinafter, embodiments of the present invention will be described. Assume that the data to be handled in parallel is N-32, which is the same as that used in the conventional example. FIG. 4 is a diagram in which a block composed of 32×32 bits is divided into units and each unit is numbered, and FIG. 6 is a diagram in which data within a unit is numbered. One block composed of 32 x 32 bits is divided into 8 bits each in the row direction and column direction as shown in Fig. 4, and as shown in Fig. 6, 8 x 8 bit data forms one unit. A case will be described in which the system is composed of a total of 4 x 4-16 units.

FIG. 6 is a block diagram of a data storage device in one embodiment of the present invention. 1 to 4 are 8 bits of input data.
Latches that take in bit by bit, latches 5 to 8 take in 8-bit data from latches 1 to 4 through 28 common buses, and latches 9 to 12 cyclically shift the 8-bit data from latches 5 to 9. The shift register % 13 controls the timing at which latches 1 to 4 output data on the common bus 28 and the timing at which latches 5 to 8 take in data on the common bus 28.
12 is an input data control circuit for specifying and controlling the amount of cyclic shift; 14 is a memory circuit composed of 32 independently operable memories so that 32-bit data can be written or read in parallel; 16 to 14; 18 is a memory circuit 14
Shift registers that take in data read out in 8-bit units and cyclically shift the data; 19 to 22 are latches that take in data from shift registers 16 to 18; 23
-26 are latches that take in 8-bit data from the latches 19-22 via the common bus 29 and organize 32-bit output data, and 27 indicates the timing and timing at which the latches 19-22 output data onto the common bus 29. , latch 2
3 to 26 are output data control circuits that control the timing of taking in data on the common bus 29 and specify cyclic shifts in the shift registers 16 to 18.

FIG. 7 is a diagram showing the address wiring of the memory circuit 14 in detail. 101 to 132 are 32 independently operable memories m1 to J2, and address input 'O+IL1
．． a2 is memory ml + m91 m+ 7 + m2
Common in 5, memory m2+ m10+ IJ8+
Common in m26... Memory m81
Wiring and address input bo so that it is common for "16 + "24 + m52.

Common for b1u memories m1 to m8, memories m9 to m
16 is common, memory h7 to m24 is common, and memory m25 to m52 is common. 1 is the remaining address input (nQ), which is wired commonly to all memories. 133 to 140 are common A read-only memory (ROM
)R, to R8, and the address value is determined depending on whether the address value given to the memory circuit 14 is handled in the row direction or the column direction. Memory R1 is memory J +
The address value ul of the 9th+mi7+m25, the memory R2 has the address value u2. of the memory m2+miO+JEITm26.・・・・・・Memory Rag memory m
8+J6, m24+m32 address value u8 is determined.

141 to 144 are each address input bo wired in common,
Read-only memory (ROM) R9 to R12 for address conversion that determines the value of b1, and determines the address value depending on whether the address value given to the memory circuit 14 is handled in the row direction or column direction. . The memory R9 determines the address value v1 of the memories m1 to m8, the address value 72% of the memory R1oH memory m9 to m+6, the memory RN determines the address value v3 of the memories m17 to m24, and the memory R12 determines the address value v4 of the memories m25 to m32.

Blocks composed of 32x32 bits are shown in Figures 4 and 6.
As shown in the figure, one unit is made up of 8 x 8 bit data, and consists of 4 x 4 = 16 units in total, and the 32 bit data in the row direction within the block is from the 1st to the 32nd tally. Assuming that the 32-bit data in the column direction is sequentially arranged from the 1st row to the 322nd row, a case will be described in which data is written from the row direction.

The input 32-bit data is sequentially decomposed into four units of 8 bits each, and 8 bits each are taken into lunches 1 to 4 in sequence. The input data control circuit 13 provides latches 1 to 4 with timing signals for outputting data to the common bus 28, and latches 5 to 8 with timing signals to take in data on the common bus 28. FIG. 8 is a diagram showing timing signals for outputting data given by the input data control circuit 13 to latches 1 to 4 and timing signals for taking in data given to latches 5 to 8. are timing signals given to latches 1 to 4, respectively, K-H
j-j are timing signals given to latches 6 to 8, respectively, corresponding to the row number within the block of input data. Figure 9a shows latches 6 to 8 corresponding to the row numbers.
FIG. 3 is a correspondence diagram of timing signals given to FIG. Based on this correspondence table, the data is cyclically shifted in units of 8 bits, and latch 5 has the numbered units (1, 1) shown in Figure 4.
.

[2,4], [3,3], [4,2] are latch 6VC
is (1+ 2)+ (2+ 1]+ (314).

(4,3), but latch 7 has (1,3:], (2+2)
, [3,1], [4,4], but latch 8 has ('1.4
], [:2. a:), [l:3,2), and (4,4) are captured. Respective data from launches 6-8 are sent to shift registers 9-12;
The data in the first row (1≦1≦8) in the unit is cyclically shifted to the right by i-1 bits according to the shift amount command from the input data control circuit 13.The data in the shift register 9 is shifted to the memory m1 to mε. , data of the shift register 10 is stored in memories m9 to m16, data of the shift register 11 is stored in memories m17 to m24, and data of the shift register 12 is stored in memories m25 to m32.

Regarding the address given to the memory, the address inputs (n,) commonly wired to all memories define a block and give a constant address value within the block.

Address values u1 to u8 for address an+a++a2(/C are handled from the row direction, all ux (1≦X≦um) are set to the same value, and 1 in each unit is
The address value of Huz=i-1 is made to correspond to the data in the row. Address human power bo.

When address values v1 to v4 for bl are handled from the row direction, all vy (1≦y≦4) are set to the same value.

The address value of Vy = j -1 is associated with the unit in the th row (1≦ko≦4) in the block. Figure 1o is a diagram showing the state in which the numbered units shown in Figure 4 are stored in the memory by the above method, and Figure 11 is a diagram showing the state in which the numbered units shown in Figure 5 are stored in the memory in the above manner. FIG. 3 is a diagram illustrating a state stored in a memory according to a method;゛In Figures 10 and 11, among the address inputs, b1 + 1) 0
The address where +a2va1·aQ is stored as the lower 5 bits is described.

In the case of writing from the column direction, the input 32-bit data 1l-j is divided into four units of 8 bits at a time, and 8 bits of data are taken into launches 1 to 4 in sequence.

The input data system circuit 13 is the same as in the row direction.

Timing signals for outputting data to the common bus 28 for launches 1 to 4 (FIG. 8 A-D) and timing signals for fetching data on the common bus 28 for launches 5 to 8 (FIG. 8 E to D) H) is given corresponding to the column number within the block of input data. FIG. 9 is a correspondence diagram of timing signals applied to latches 5 to 8 in correspondence with column numbers. From this correspondence table, the units numbered as shown in FIG. 4, which are the same as in the case of the row direction, are taken into the latches 6 to 8. The respective data from latches 5 to 8 are sent to shift registers 9 to 12, and each shift register 9 to 12 receives a shift amount command from the input data control circuit 13, and the first column in the unit (1≦1≦ 8) data is 1-1
Cyclic shift bits to the right. The data of the shift register 9 is stored in the memories m1 to IJ, and the data of the shift register 1o is stored in the memories m9 to m16. Data of shift register 11 is stored in memory m1 full m24%/data of shift register 12 is stored in memories m25 to m32.

Regarding addresses to be given to memories, the number of address inputs commonly wired to all memories defines a block, and as in the row direction, a constant address value is given within the block. Address input 'O+ aj +
When handling from the column direction, ux (1≦X≦8) for IL2 is uz for the data in the first column in the unit.
=mod6 (a-i+x) +7) 7 dresses are made to correspond. FIG. 12 is a diagram showing column numbers within a unit and corresponding address values u1 to u8. Address value Vy for address manual power bo, b (1≦y≦4)
When handling from the column direction, the 5th row in the block (1≦
)≦4) Vy: m Od4(4)
+y) addresses. Figure 13 shows the column number of the unit in the block and the corresponding address value v.
It is a figure showing 1-v4. When data is stored in the memory using the above method, the data can be allocated and stored in the memory in exactly the same way as shown in FIGS. 10 and 11, which show the case of writing from the column direction.

Next, the case of reading data will be explained.

When reading 32 bits of data in the 1st row direction, the data in the blocks shown in FIGS.
Since the data is stored as shown in the figure, regarding the address given to the memory, the 10 address inputs commonly wired to all the memories define a block and give a constant address value within the block. Address input aOr
Address values u1 to u8 for 'l + '2 are handled from the row direction, making all losses (1≦X≦8) the same value, and setting the first row (1≦1≦8) in each unit to the same value. The address value of nuz = i-1 is input to the address input bo for the data.

When handling address values v1 to v4 for bl from the row direction, all Vy (1≦y≦4) are set to the same value, and vy is set to the unit in the third row (1≦j≦4) in the block.
= gives the address value of code 1 and reads data from memories m1 to m42 (data from memories m1 to m8 is read from the shift register 16, data from memories m9 to m+6 is read from the shift register 16, and data from memories J7 to m24 The data from the memories m25 to m32 are taken into the shift register 17, and the data from the memories m25 to m32 are taken into the shift register 18.

Since the data taken out to the shift registers 16 to 18 is stored in a cyclic software 71 corresponding to the row number within the unit,
Each shift register 15-18V? : , by the shift-j, i command from the output data open side 1 circuit 27,
Data IJ, i-1 bits in the first row in the unit are cyclically shifted to the left to return to the original state, and then sent to the launches 19 to 22, respectively. The 32-bit data of 8 bits each taken into latches 19 to 22 is the row number (
Since it is cyclically shifted in units of 8 bits corresponding to the banknotes +'J, ) of the unit, in order to return to the original state, the output data control circuit 27 is connected to the common bus 29 for the latches 19 to 22. A timing signal for outputting data is given to the latches 23 to 26, and a timing signal for taking in data on the common bus 29 is given to the latches 23 to 26. The data output timing signals given by the output data control @1 circuit 27 to the latches 19 to 22 are shown in FIGS. Figures 8 E-H are given corresponding to the numbers. 14th
Figure a is a diagram showing the timing signals applied to the latches 23 to 26 in accordance with the row numbers. As a result, lunch 2
32-bit data from 3 to 26 is 32 bits in order from the first column.
It can be taken out in a row.

When reading 32-bit data in the column direction, nQ address inputs commonly wired to all memories define a block, and give a constant address value within the block. When handling from the column direction, ux (1≦X≦8) for address input 'O+a1+a2 is the i-th column (1≦1≦8) in the unit.
) shown in Fig. 12 for the data of u, (= m od
Enter the address of B (8-i+X) into the address input bo
, the address value vy (1≦y≦4) for b1 is the j-th row (1≦j≦4) in the block when handling from the column direction.
vy = m o d4 (4:l
+1) and reads data from the memories m1 to m52. The data taken into the /ft registers 16 to 18 is the same as when taken out from the row direction.

Since the data taken out to the shift registers 16 to 18 is circulated/shifted in accordance with the column number within the unit, the output data system is changed in each shift register 16 to 18.
According to the /ft amount command from the circuit 27, 1 in the unit
The data in the column is cyclically shifted 1-1 bits to the left to return to its original state and sent to latches 19-22, respectively. As in the case of the row direction, the 32-bit data of 8 bits each received by latches 19 to 22 is cyclically shifted in 8-bit units corresponding to the column number within the block (column number of the unit). Therefore, in order to return to the original state, the output data control circuit 27 (l''j: a timing signal for outputting data to the common bus 29 for the latches 19 to 22 (FIG. 8A)
-D), a timing signal for fetching data on the common bus 28 for the latches 23 to 26 (Fig. 8 1+knee H)
is given corresponding to the column number within the block of data to be read. Figure 14 shows latches 19 to 2 corresponding to the row numbers.
FIG. 2 is a correspondence diagram of timing signals given to FIG. As a result, 32-bit data can be extracted from the lunches 23 to 26 in a sequentially arranged manner from the first line to the 32nd line.

By the above-described operation, 32 bits of data from one row direction and data from a column direction can be written and read in parallel.

In the embodiment described above, the data in the first row (column) of the unit is shifted by i-1 bits cyclically, but for example, the data in the first row (column) is shifted by n1od8(i+2).
Data may be stored by shifting bits. It's a trench.
The same applies to the cyclic shift of 8-bit units within a block. It is cyclically shifted to the right when inputting, but it can also be cyclically shifted to the left.

Address input aO+a when handling data from the column direction
The address values u1 to u8 for L+a2 are all the same value and are converted when handling data from the row direction, but the reverse is also possible. The same applies to address values v1 to v4 for address inputs bo and b1.

When writing and reading all data in 32-bit increments at high speed at the same processing speed from both the row and column directions.

All data is divided into 32 bits each in the row direction and column direction.
It is sufficient to divide the data into 2×32 blocks and perform the operations described in the previous embodiment within the valley blocks.

Effect of the invention The present invention provides the following effects.

(1) 2n1+n2 focus data 2 hits each 2
By decomposing the data into n2 units, cyclically shifting the 2n1-bit data in bits within the unit, and cyclically shifting it in 2-bit units, it is possible to reduce the parts that require high-speed operation. I can do it.

(2) 2 memories ml +
"2 +""'+ m2n4+12 address input a
Or 2L1+ "'-2"yl), address values u1 to u2n for n1 pieces of -+, and address input b0
+ bll ”'”'+ n2 pieces of bn2-1
It is sufficient to simply convert the address values v1 to v2n2 of yJLC, and the circuit scale required for address management is reduced.

(3) Even if the data 2n1+n2 to be handled in parallel increases, the circuit scale required for address management only increases in proportion to 2n1+2n2.

[Brief explanation of the drawing]

Figure 1 is a data layout diagram showing numbered 32x32 bit data, Figure 2 is a data layout diagram showing conventional data allocation to memory, and Figure 3 is a data layout diagram showing conventional data allocation in the column direction. Figure 4 is an address diagram showing the address values given to each memory when handling the I'i1 pronk. Figure 6 is a unit number arrangement diagram in which data consisting of 32 x 32 bits is divided into units and each unit is numbered. FIG. 6 is a block diagram of a data storage device in an embodiment of the present invention, FIG. 7 is a detailed circuit diagram of the memory circuit 14, and FIG. 8 is a data layout diagram in which data within a unit is numbered. Timing diagram provided by the side diagonal circuit (output data spread circuit) to the latch, No. 9
Figures a and b are correspondence diagrams showing the correspondence of timing signals given to latches during writing in the row and column directions, Figure 1o is a memory layout diagram showing the allocation of units to memory in the present invention, and Figure 11 is a diagram of the present invention. FIGS. 12 and 13 are memory layout diagrams showing how the data in each unit in the invention is allocated to memory in the above-described manner. Addresses u1 to u8 and address value v1 given to memory
14A and 14B are correspondence diagrams showing the correspondence of timing signals applied to the latches during readout in the row direction and column direction. 1-8... Latch, 9-12... Shift register, 13... Input data planning circuit, 14
...Memory circuit, 16-18.../Foot register, 19-26...Latch, 27...
...Output data system m+ circuit, 28.29...
Common lotus. Name of agent: Patent attorney Toshio Nakao and 1 other person No. 1
Figure 2 "I=mOdl? (β-cx+33) @ 4 Figure 5 @ 6 Figure Input F-G Figure 8 6 Run + ((Run + jQ) B Latch 2 (Runner 20) C Run + 3 ( Latch 2f) p Run ÷ 4 (Latch 22) Figure 9 Figure 10 Figure 12 Figure 13

Claims (1)

[Claims] n1+n2 2 bits each in row direction and column direction, total n1+n2
Data composed of n1+n2 total 2 × 2 bits is considered as one block, and the data in the block is arranged in the row direction,
Divided into 2n1 bits in the column direction') s 2
” x 2” t bits of data as one unit
For 2-bit input data in the row direction (or column direction) n1+12 in the block composed of n2×2n2 units, 2n1-bit data is generated in each of the 2n2 units to which the input data belongs. means for cyclically shifting a predetermined amount in bit units in correspondence with the occupied position, and cyclically shifting the predetermined amount in 2n1 bit units in correspondence with the positions occupied by each of the 2n2 units to which the input data belongs within the block; means for rearranging data by a means; and two independently operable means for storing the rearranged input data.
n1+n2 memories J+m2+...l m2
n1+n2, and the previous nl+n2 two memory addresses aQ l aj +.
....r ``For n1 pieces of n, -1, address value u1 is input by common address input of each memory m2n18, +1, and address value u1 is input by common address input of each memory m2n10.+2. u2 is input,・
..., each of the memories m2n1. Wire and address input bD+bi+...+ so that the address input of i+2n1 is shared and the address value u2n is input.
Regarding n2 pieces of '112-1, the address input of each memory m is common and the address value v1 is input,
Address value v2 is input by common address input of each memory "z" i+j, ......, each memory m
A memory circuit wired so that the address input of n2 ・ is input in common and the 2n+(2−ri+ core address value vn2) is input, and the address value ux is connected to the data from the row direction (column direction) in the block. Means for setting the same value according to the data position when writing/reading, and setting to an individual value according to the data position when writing/reading data from the column direction (row direction), and the address value Vy is set to the same value according to the data position when writing or reading data from the row direction (column direction) within the block,
When writing or reading data from the column direction (row direction), means for setting individual values according to the position of the data, and means for setting 2-bit data in the row direction (or column direction) in the read block. On the other hand, it is decomposed into 2n2 units of 2n1n1+n2 bits, and the data is divided into 2n2 units corresponding to the position that the read data occupies in the block.
means for cyclically shifting the hint data by a predetermined amount in units of bits within the decomposed unit; and means for cyclically shifting the predetermined amount in units of 2 bits; A data storage device characterized in that writing and reading of 2 hits of data in the row direction and 2 hits of data in the column direction can be performed in parallel for 2n1+n2 bits. however. n1≧1 n2≧1 0≦i≦2−1 1≦j≦2n1 1≦X≦2n1 1≦y≦2n2 Awesome Nb乎