JPS6142046A - Data storage device - Google Patents

Abstract

PURPOSE:To read out and write at a high speed both data of a line direction and data of a row direction by delimiting input data to the line direction and the row direction at every N1 bit, and executing rearrangement of the data by a position occupied by the N1 bit. CONSTITUTION:Data which is inputted is resolved into three units in order, for instance, as to 4 bits each, inputted to latches 8-10 by a timing signal. Also, the data is brought to a round-shift by a 4 bit unit, and units (1, 1), (2, 3), (3, 2), and (1, 2), (2, 1), (3, 3), and (1, 3), (2, 2), (3, 1) are inputted to a latch 11, a latch 12, and a latch 13, respectively. In data substituting circuits 2-4, an input data is rearranged based on a line number in the unit under a control from an input data controlling circuit 14, and written successively in a memory 1. In case of read-out, it is executed in the almost same way by reversing the preceding steps.

Description

[Detailed Description of the Invention] Industrial Application Field The present invention can write data from both row and column directions at high speed, and read reduced data from both row and column directions. The present invention relates to a data storage device that can be used at high speed.

Conventional configuration and its problems N=N1×N2 (N1=2n1) memories that can operate independently write and read data from the column direction and row direction in N bits, and the reduction rate is an index of 2. As a method that can read N bits of data reduced in parallel from the column direction and the row direction in the case of multiplication, the reduction rate is up to N5.
=2n30: all data in row direction and column direction respectively M=
Divide into NxN3 bits, take a block composed of MxM bits as a processing unit, sample the data in the same row and column in the block every 2h (0≦h≦n3) bits, and calculate the results every N bits. When the data is divided into groups, the data in each group may be allocated and stored in N memories so that they are not allocated to the same memory.

The data in the same row and column in the block is 2h(O
≦h≦r13) The result of sampling every bit is N
As a method for allocating and storing data in each group in different memories when the data is grouped by bit, consider the case where N=12°n3=1, for example. The first 12 bits of data in the i-th row (i = 1 to 12) in the block are cyclically shifted by i-1 bits, and the data in the i-th row is stored at address 48ko+i-1 in each memory. =1~
The 12-bit data after 12) is cyclically shifted by i bits, and the i-th row data is stored in 48 of each memory as 0+1+11.
The first 12 bits of data in the i-th row (i = 13 to 24) are cyclically shifted 1-12 bits, and the data in the i-th row is placed in each memory at address 0+i+11, and the data is covered in the i-th row. The 12-bit data after =13-24) is 1-11
The data in the i-th row is cyclically shifted by bits into the 4th row of each memory.
Assigned to address 8, 0+1+23! 2 Memorize.

Fig. 1 is a diagram showing numbered 24x24 bit data, and Fig. 2 is a diagram showing data stored in memories m1 to -12 when the data in Fig. 1 is allocated in the above method. .

Figure 3 is a diagram showing the lower address values given to the memory when writing and reading in one column direction when data is allocated to each memory as shown in Figure 2.
In writing and reading in the column direction, lower address values given to the memory are given different values one by one. The same holds true when data is reduced to S and read out. For this reason, it is necessary to provide each memory with an address that has been subjected to address conversion processing, and there is a drawback that the circuit scale required for address conversion processing of the memory increases in proportion to N.

Purpose of the Invention The purpose of the present invention is to operate independently N = N, XN2 (N
1 = = 2l) memories, the data from the row direction and from the column direction is written and read in parallel N bits each, and the data from the row direction and column direction is reduced by an exponential power of 2. An object of the present invention is to provide a data storage device which can read out data reduced in parallel in N bits at a time, and in which address conversion processing for the memory is simple.

Structure of the Invention In order to achieve the above object, the present invention deals with 7"-
E75EN=N, xN2(N, =2n1)"c' If the maximum reduction rate when reading is N5=23, the memory mm
... rnN address human power @o, -ml
r2? For n1 pieces of "P" nl-1, memory m (210, .

l-21-j)・e(0≦l≦n, -1, 1≦l≦21
-○, 0≦1≦2 -1.1≦e≦N2) address input・
is common, memory (21+1.i I),. Wiring so that address input al is common, address input bO'
For each n3 pieces of `` `` ``bn3-1 and 'O#''''#Cn-1, the memory m(2t + 1).

P-2-(Zn,.(0≦8≦n3 1 .1≦p≦
n21 tO≦q≦2 −1. t is the remainder when 8 is divided by n) Address input b8 and C8 are common, memory
(2t +1.

For the remaining addresses d0 to dn, the memories mN1(.-1)+, to mN10. The address value given to the memory is made to correspond to the data position at the time of writing and reading.

Regarding storing data in memory, MxM (M=NxN
3) In the row direction within a block composed of bit data,
Separate every N bits in the column direction p, make one subblock with N x N bit data and form N3 x N3 subblocks, divide the data in the subblock every N1 bits in the row direction and column direction, N,x
N, bits of data as one unit N2XN2
For N-bit input data in the row direction (or column direction) within a sub-block, the position occupied by the 'P41 pit data in each unit to which the input data belongs and the input data within the block constitute a unit. This method involves rearranging the data in accordance with the position occupied by the sub-block to which the input data belongs, and cyclically shifting a predetermined amount in units of N2 bits in correspondence to the position occupied by the unit to which the input data belongs within the sub-block. Sort the input data and allocate and store it in memory.

DESCRIPTION OF EMBODIMENTS Hereinafter, embodiments of the present invention will be described. Assume that the data handled in parallel is KN=12, as in the conventional example, and the reduction is up to %.

12 blocks consisting of 24x24 bit data
The data is divided into sub-blocks consisting of data of 12 x 12 bits, and the sub-blocks consisting of 12 x 12 bits are further divided into units consisting of 4 x 4 pits. Fourth
The figure shows the numbering of divided subblocks, No. 6
The figure shows the numbering of units within a sub-block.
FIG. 6 is a diagram in which data in the unit 7) is numbered.

FIG. 9 is a block diagram of a data storage device according to an embodiment of the present invention.

1 is a memory circuit composed of 12 independently operable memories m1 to m12, and memory circuit 1 serves as an address input. , al, the memory m1. m3゜0115 p
n17 P fEl g, common ao of ml 1 (uo is its address value), In2 y n14
y mB t mB p fnl□, a of ml 2
O is common ('Vo is its address value), ml, m2.
mB.

mB, m9. ml. common al (ul is its address value), n13 t n14 F 1n7 t m
B # m11 p common al of n112 (vl
is its address value) K wiring. Regarding addresses b0 and C0, memory m1. m3゜m5, rn7
, fng r rn 11 bO and C+0 are common (x.

and Vr□ is its address value), m22m4. mB, m
B.

! n 10 #r! 112 bo and C0 are common (y
□ and zo are the address values) in common, and the remaining addresses d0 to dn are connected to the memories m1 to m4.
common (rl is its address value), memories m5 to m8
(C2 is its address value), memory m9~”12
are wired in common (rs is its address value).

FIG. 8 is a diagram showing the address input wiring of the memory circuit 1 in detail.

2 to 7 are data replacement circuits that rearrange data, and Pl performs the replacement of 1 and 2 degrees, 3 and 4 data of four data arranged in order, 1 and 3 degrees, 2 and 4 data. After performing the replacement P2 and replacing P, the replacement P
When the synthetic permutation that performs 2 is represented by P3, and the identity permutation that does not replace data is represented by Po, data permutation circuits 2 to 7
performs any one of these substitutions from P0 to P3 according to the control signal. FIG. 9 is a diagram showing data rearranged by permutation pk (o≦≦3).

8 to 10 are latches that capture input data, 11 to 13 are 2
Latches 14 each take in data from latches 8 to 1o via the common bus 24; replacement P performed by the data replacement circuits 2 to 4; timing at which the latches 8 to 10 output data onto the common bus 24; and latch 11. -13 are input data control circuits that control the timing of taking in data on the common bus 24, 16-17 are latches that take in data, and 18-2° are input data control circuits that control the timing of taking in data on the common bus 24; A latch to take in, 21 indicates the timing at which the replacement P1 latches 15 to 17 output data onto the common bus 25, the timing at which the latches 18 to 2o take in data on the common bus 26, and 22, which is performed by the data replacement circuits 5 to 7. This is an output data control circuit that controls the reverse shuffle circuit.

When the reverse shuffle circuit 22 is reduced and read out, the 12 pieces of data become a shuffled arrangement, and this circuit is used to convert this arrangement into the original arrangement. Sort and output the data as shown,
When reading without reduction, data is output in the same order.

Reference numeral 23 is an address generation circuit, which determines whether the data should be handled in a reduced size or not, based on the position (coordinates) of the block of data to be handled and the position (coordinates) within the block. Address value uO1u11volv1 given to memory circuit 1 when handling data V? ! W, 3F
Z r ”-C3 is created.

0FOO'O#1 The data of the 12 pits in the row direction of the sub-block composed of 12x12 focus are the 12 pits in the row direction from the 1st column to column 1].
Assuming that the bit data is arranged in order from the first row, we will first explain the case of writing data from the row direction.

The input data is sequentially broken down into three units of 4 bits each, and 4 bits each are taken into latches 8 to 1o. The input data control circuit 14 is connected to a common bus 2 for the latches 8 to 10.
The timing signal for outputting data to latches 11 to 1
A timing signal for fetching data on the common bus 24 is given to the terminal 3. FIG. 11 shows the timing signals that the input data control circuit 14 gives to the latches 8-1° and the latches 11-1.
11A-C are diagrams showing the timing signals given to the
are timing signals given to latches 8 to 10, respectively, and D
-F is a timing signal given to latches 11 to 13, respectively, corresponding to the row number within the subblock of input data.

FIG. 12 is a diagram showing timing signals given to the launches 11 to 13 in correspondence with the row numbers. This results in data of 4
The latch 11 is cyclically shifted in units of pits, and the numbered units (1p') P C2+3 shown in FIG.
)t (jr2), but the latch 12 has (1#2)l (
2#1)# (3rs), but latch 13 has (1t3)
t (2,2)t[3,1] is taken in.

Data replacement circuits 2 to 4 input data from latches 11 to 13, and under the control of the data control circuit 14, the data in the units in subblocks <1.1> and <2, 2> are processed as described above. Replacement P0. P1. P2. P
3 and the line number within the input data unit, and rearrange the input data. Sub-block 1, 2>
And for the data in the unit in 2,1>K, the above permutation P1. P0. P3. The input data is rearranged by sequentially pairing P2 with the line number within the input data unit.

The data rearranged using the above method is stored in memories m1 to m.
Write to 12.

Regarding the address given, address input and. .

and the address value U for. tul is 1 in each unit
0'' for the line, w1# for the second line.

The third line is "2l", and the fourth line is 13" (ulu.

(in decimal notation), and the address value v0. v1 is v0=
u0. It is input to the memory circuit 1 as v1=u1.

Address value x0 for address b0 and address value y0 for address C are subblocks (1, 1)
Then xo=yo=0, and in subblock <1, 2> “O
='t yQ =o, x in subblock <2.1>
O=o, yo=1, X o in subblock <2.2>
"7o" 1 is given, and the address values WO and zO are W
Input O="Ol zO="0 to the memory circuit 1.

Address values r1~ for the remaining addresses d0~d
Set r3 to the same value KL, "31" for the first row unit in the subblock, and "3j-1-1" for the second row unit.
, give @3j+2″ (j is the block position) to the unit on the third line.

FIG. 13 is a diagram showing a state in which the data in the numbered blocks shown in FIGS. Diagram showing the state of storing in memory according to the method, same (b)
2 is a diagram showing a state in which data in each unit is stored in a memory in correspondence with the position of a sub-block. FIG. In Figure 13, among the address inputs, C01bO"1j"o is the lower 4
The addresses where bits d0 to dn are stored as upper bits are described.

Next, the case of writing from the column direction will be explained.

Sort the input data and store it in memories m1 to m1.
The operation of writing to 2 is the same as the writing from the row direction, except that the row number is changed to the column number.

Regarding the given address, the address value u0.u1 for the address input "o tal" is subblock < 1.1
) and <2, 2> for each unit, '0' for the first column, '1' for the second column, '2l' for the third column, @3'' (ul uo in decimal), "1" in the first column in each unit of subblock <1.2) and subblock <2.1), @0" in the second column, 3ta 11
3″ for the eyes.

@2" is given to the fourth column, and address values V. and v1 are input.

Address value I for address input b0. , wo, the address value yot for the address c0.

is the same as when writing from the row direction.

Address values r1~ for the remaining addresses d0~d
r3 is the unit in the first column in the sub-block, r,
=3j, r2=35+1, r3=31+2.The unit in the second column has r1=3j-1-2, r2=3j, r3
=3++1.The third unit has r1=3 j+
1, r2=31+2.

Give r3=3 i (j is the position of the block).

FIG. 14 is a diagram showing column numbers within a subblock and corresponding address values given to each memory.

When data is stored in the memory using the method described above, data can be allocated and stored in the memory in exactly the same way as shown in FIG. 13, which shows the case of writing from the row direction.

Next, the case of reading data will be explained.

First, when reading 12-bit data in the row direction without reduction (standard), the probes shown in FIGS. 4 to 6 are used.

Since the data in the memory is stored as shown in FIG. 13, the address given to the memory is given in the same manner as in the case of writing from the row direction, and data is read from the memories m1 to "12."

Regarding rearrangement of data, the operation is the reverse of that at the time of writing. Since pk is the inverse permutation of the above-mentioned permutation pk, the data permutation circuits 6 to 7 change the data permutation circuits 2 to 4 at the time of input according to the data position in the subblock and unit under the control from the output data control circuit 21. perform the same action as the one performed.

The 12-bit data, 4 bits each, taken into latches 15 to 17 is cyclically shifted in units of 4 pits corresponding to the row number (row number of the unit) within the subblock, so it is returned to its original state. In order to restore the data, the output data control circuit 21 provides the latches 15 to 17 with a timing signal to output data to the common path 26, and the latches 18 to 2o with a timing signal to take in the data on the common bus 26. The timing signals that the output data control circuit 21 gives to the latches 16 to 17 are shown in FIGS.
The timing signals D to F in FIG. 11 are respectively provided in correspondence with the row numbers within the sub-block of the data to be read. Figure 15 shows latches 18 to 2o corresponding to the row numbers.
FIG. 3 is a correspondence diagram of timing signals given to FIG.

The reverse shuffle circuit 22 reads data in the row direction in parallel by outputting the 12-bit data as is from the latches 18-20.

When reading 12-bit data in the column direction (standard) without reduction, the address given to the memory is given in the same way as when writing from the column direction, and data is read from memories m1 to m12. Read out.

The operation of rearranging the read data is the same as in the case of reading from the row direction, except that the row number is changed to the column number, and data in the column direction can be read in 12 bits in parallel.

Next, a case will be described in which 12-bit row data in a block reduced to 5A is read out. In this case, assume that odd-numbered data in each row is extracted.

Regarding the address to be given, the address value uo p ul for the address input "o pal" is the address value "uo p ul" for the data in the first row (1≦1≦24) in the block.
o (uluo is expressed in decimal, 10 is the remainder when dividing 1-1 by 4), and the address value vOtv1 is vO=uO, v
1=u1 and input to the memory circuit 1.

The address is human power. The address value I0 for K and the address value y0 for address c0 are 1 to 12 in the block.
When reading data in odd-numbered rows up to the row, x0=y0=0
, when reading data of even numbered rows from 1st to 12th rows in a block, x0=1°y0=0, 13th to 24th rows in a block
When reading data in odd-numbered rows up to the row, l0=70=1
, when reading data from even-numbered rows from 13th to 24th rows in a block, give x=o, y0=1, and use the address value "o*
"o inputs W○=xo and zo=yo to the memory circuit 1.

Address value r1 for the remaining addresses d0 to dyu
~ Set r3 to the same value and line 1 to 4 in the block and 13~
13j″ for line 16, lines 6-8 and 17-20
@3j+1″ for the row.

"33+2" (j is the block position) is given to the 9th to 12th lines and the 21st to 24th lines.

FIG. 16 is a diagram showing row numbers within a block and their corresponding addresses when the data is reduced to a month and read in the row direction.

Regarding the operation of rearranging the read data, the data replacement circuits 6 to 7 perform Po replacement for the 1.5th, 9th, 14th, 18th, and 22nd lines in the block under the control from the output data control circuit 21. , 2゜6.10,13,17,2
For the first line, replace Pl, 3, 7, 11.16, 2
For lines 0 and 24, P2 substitution, 4, 8, 12. i
6. -+9.2. For the q-th row, P3 is replaced.

The 12-bit data of 4 bits each taken into latches 16 to 17 is cyclically shifted in 4-bit units corresponding to the row number within the block. The output data control circuit 21
Timing signals applied to latches 18-20 in FIGS. 1A-C correspond to the row numbers within the block of data to be read, respectively, as shown in FIGS. 11D-F. FIG. 17 is a diagram showing timing signals applied to latches 18 to 20 in accordance with row numbers.

When the reverse shuffle circuit 22 rearranges the 12-bit data from the latches 18 to 20 as shown in FIG. 10 and outputs it, the odd-numbered data in the row direction can be read out in parallel by 12 bits.

FIG. 18 is a diagram showing data output from the reverse shuffle circuit 22 after being rearranged in order with the data read from the memory circuit 1 in the case of 3AK reduction and reading in the row direction.

Next, a case will be described in which 12-bit column-direction data in a block reduced to 10% is read out. In this case, assume that odd-numbered data in each column is extracted.

Regarding the address to be given, the address value uO2u1 for address input "09a1" is u0=o, 1 in the block.
．． 2, 5, 6. ..., 21,228, ..., 23.
For the data in the 24th column, u1=1 is given, and the address values vo, v1 are input to the memory circuit 1 as vo=uo, v1=u1.

Enter the address. The address value I0 for K and the address value y0 for address c0 are 1 to 12 in the block.
When reading data in odd columns up to column xo=70=0
When reading the data of even numbered rows from 1st to 12th rows in one block, l0=1°y0=0, 13th to 24th rows in the block
When reading data in odd-numbered rows up to the row, x0=70=1
, when reading data in even-numbered rows from 13th to 24th rows in a block, l0=0. Give y0=1, address value),
zo inputs 1="op zo =70" to the memory circuit 1.

Address values r1 for the remaining addresses d0 to dn
~r3 is rl ``” 3 j p r2 = 3 for the 1st to 4th columns and 13th to 16th columns in the block.
j 11 t r3 ==3] +2, r3''3j+1, r1= for the 1st to 4th tari in the block
3 j +1 pr2 ” 31 + 2 + '3
= 31 (+ is the position of the block) is given.

FIG. 19 is a diagram showing column numbers within a block and their corresponding addresses when the data is reduced to 34 and read in the column direction.

Regarding the operation of rearranging the read data, except for changing the row number to the column number, it is the same as the case of reading after reducing 3AK from the row direction, and the odd numbered data in the row direction is read in 12 bits in parallel. I can put it out.

By the above-described operation, writing of data from the row direction and data from the column direction, standard readout, and readout reduced to 12 pits can be performed in parallel.

In the embodiment described above, odd-numbered data is taken out during reduction to %, but even-numbered data can also be taken out in the same way by changing the address given to the memory circuit 1.

When writing and reading all data in 12-bit blocks at the same processing speed from both the row and column directions, the data is divided into 24 x 24-bit blocks of 24 bits each in the row and column directions, and each block is The operation described in the above embodiment may be performed.

When reading data reduced to 1/2h (h≧2), it can be performed in the same way by extending the operation described in the previous embodiment.

Effect of the invention The present invention provides the following effects.

(1) N notes that can operate independently') full,
m2 F...TnN address input "01...t
Address conversion for n1 pieces of an, -1, address input bOf @' ?bn-1 and 'O' ” -
' Address conversion for each n3 lines of cn31 and remaining address manpower d. It is only necessary to perform address conversion regarding -dn, and the circuit scale required for address management is reduced.

Even if the maximum reduction rate becomes 1/2n3, the circuit scale required for address management only increases in proportion to n3.

(3) Permutation Pk that rearranges data (o≦to≦n1
Since the inverse replacement of 1) is Pk, it is possible to share the data replacement circuit for writing and reading.

[Brief explanation of the drawing]

Figure 1 shows numbered 24x24 bit data, Figure 2 shows the conventional allocation of data to memory, and Figure 3 shows the conventional allocation of data to memory in the column direction. A diagram showing the address values given to each memory during handling, Figure 4 is a diagram with numbering of divided subblocks, Figure 5 is a diagram with numbering of units within a subblock, and Figure 6 is a diagram of units. 7 is a block diagram of a data storage device in an embodiment of the present invention, FIG. 8 is a detailed diagram of the memory circuit 1 in FIG. 7, and FIG. 9 is a diagram showing the replacement P. FIG. 10 is a diagram showing data that has been reverse shuffled, and FIG. 11 is a diagram showing data that has been rearranged by applying
A diagram showing the timing signals given to the latches 11 to 13 (18 to 20) by the input data control circuit 14 (output data control circuit 21), and the timing signals given to the latches 11 to 13 (18 to 20) during writing. 13A and 13B are diagrams showing the allocation of data to memories in the present invention, FIG. 14 is a diagram showing address values given to each memory when handling from the column direction, Figure 15 shows the latches 18 to 18 during standard readout.
FIG. 1e is a diagram showing the address values given to each memory when read out in the row direction after being reduced to %, and FIG. Correspondence diagram of timing signals given to 2o, 1st
Figure 8 shows the seventh case in the case of 3AK reduction and reading in the row direction.
FIG. 19 is a diagram showing data read from the memory circuit 1 and data from the same-way shuffle circuit 22, and FIG. 19 is a diagram showing address values given to each memory when the data is reduced to % and read in the column direction. 1...Memory circuit, 2-7...Data replacement circuit, 8-13...Latch, 14...
...Input data control circuit, 15-20...Latch, 21...Output data control circuit, 22...
. . . Reverse shuffle circuit, 23 . . . Address creation circuit, 24, 25 . . . Common bus. Name of agent: Patent attorney Toshio Nakao and 1 other person No. 1
Figure 2 Pictorial Area -6F, , , , 4 -
Figure 5 Figure 6 Figure 7 Figure 7 Entrance 1-J Figure 9・・Convex Masa Niko・Masashi Anonymous=■ Fig. 10■■Work ■Ko ■Digaku I Ward Masa ■Masa [Person King=Ko Fig. 11A
La,,chi8 (15),

La,,chi 10 (/7) Figure 12 Figure 13 ar Figure 13/bl "l #, #J M. Figure 14 Figure 15 Figure 16 Figure 17rgJ 18 Cause Figure 19

Claims (1)

[Claims] All 2^l^+^1・i of 2^(n_1) pieces of data
-2^l-j data and 2^l^+^1・i-j data are replaced by P_(2^l), which is obtained by successively performing a different permutation P_(2^l) When all the permutations P_k obtained when the composite permutation is P_m and the identity permutation that does not exchange data is P_o are elements of the permutation set, the row direction and column direction are each N_1 × N_2 × N_3 bits. The data in the block consisting of N_1×N in the row direction and column direction, respectively.
Divide every _2 bits, (N_1 x N_2) x (N_
1 x N_2) bits of data constitute one sub-block, the data within the sub-block is divided into N_2 bits each in the row direction and column direction, and the sub-block consists of N_1 x N_1 bits of data forming one unit. For input data of N_1×N_2 bits in the row direction (or example direction), the input data is replaced according to the position occupied by the N_1 bit data in each unit and the position occupied by the subblock in the block. means for rearranging the data in a one-to-one correspondence between the elements of the set; and means for cyclically shifting a predetermined amount in units of N_1 bits in correspondence with the position occupied by the unit to which the input data belongs within the sub-block. A means for rearranging data, and N_1×N_2 independently operable memories m_1, m_2, . . . for storing the rearranged input data.
m_N__1_+_N__2, and n_1 of address input a_o, ..., a_n__1_-_1 of each memory.
Regarding books, memory m_(2^1^+^1)_・_i
＿−＿(2＾l)＿−＿j＿]＿・＿e address input a_l is shared, address value u_1 is input, memory m
＿[＿(2^l^+^1)＿・＿i＿−＿j＿]＿・＿
Address value v_l using common address input a_l of e
Wiring and address input b_o, ..., b
＿n＿＿3＿＿−＿＿１ and c_o,...,c_n＿＿3
For each n_3 pieces of ____1, the memory m_[_(2
^t^+^1)＿・＿p＿−＿(2＾t)＿−＿q]＿
・The address inputs b_s and c_s of _e are input in common, and the address values x_s and w_s are input, and the memory m_[_(2
^t^+^1)＿・＿p＿−＿(2＾t)＿]＿・＿e
For the remaining address inputs d_o to d_n, the memory m_N_
＿１＿(＿e＿−＿１＿)＿＋＿１〜m_N＿＿１＿・
A circuit wired in common only for _e and the address value u_l
, v_l, x_s, y_s, w_s, z_s and the respective address values r_g regarding the address inputs d_o to d_n are input values according to the data position and direction during writing or reading and the reduction rate 1/2^h during reading. and a means for performing one of the permutations P_k on the read N_1×N_2 bit data in the row direction (or column direction) in the block in correspondence with the data position in the block to arrange the data. The method includes means for rearranging data by shuffling, means for cyclically shifting a predetermined amount in units of N_1 bits, and means for restoring based on data shuffled during reduction, Writing data in the direction and column direction, reading data in the row direction and column direction within a block at a reduction rate of 1/2^h is N_
A data storage device characterized in that it can perform 1×N_2 bits in parallel. However, o≦l≦n_1-1 1≦i≦n_1-1-e o≦j≦2＾l-1 o≦k≦2＾(n_1)-1 N_1=2＾(n_1) N_3=2＾( n_3) 1≦e≦N_2 o≦s≦n_3-1 1≦p≦2^(n_3)^-^1^-^t (t is s
(remainder when divided by _1) o≦q≦2＾t−1 1≦h≦n_3.