JPS61102702A - Chip-shaped electronic component - Google Patents

Chip-shaped electronic component

Info

Publication number
JPS61102702A
JPS61102702A JP59225475A JP22547584A JPS61102702A JP S61102702 A JPS61102702 A JP S61102702A JP 59225475 A JP59225475 A JP 59225475A JP 22547584 A JP22547584 A JP 22547584A JP S61102702 A JPS61102702 A JP S61102702A
Authority
JP
Japan
Prior art keywords
nickel
layer
chip
electroplating
film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP59225475A
Other languages
Japanese (ja)
Inventor
紫芝 忠司
嗣郎 太田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Koa Corp
Original Assignee
Koa Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Koa Corp filed Critical Koa Corp
Priority to JP59225475A priority Critical patent/JPS61102702A/en
Publication of JPS61102702A publication Critical patent/JPS61102702A/en
Pending legal-status Critical Current

Links

Landscapes

  • Fixed Capacitors And Capacitor Manufacturing Machines (AREA)
  • Details Of Resistors (AREA)
  • Non-Adjustable Resistors (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【発明の詳細な説明】 (産業上の利用分野) 本発明は、プリント配tQ基板等に搭載されるチップ抵
抗器やチップコンデンナ等のチップ状電子部品にかかり
、その゛上極部の構成に関する。
Detailed Description of the Invention (Field of Industrial Application) The present invention relates to chip-shaped electronic components such as chip resistors and chip capacitors mounted on printed Q-boards, etc., and relates to the structure of their upper poles. .

(従来の技術) 従来、例えばチップ状抵抗器などの電極形成に際しては
、銀とパラジウムよりなるペースト又は、銀とガラスの
ペーストを1個1個チップ片の端面の電極形成部に塗布
し、これを焼成して半田メッキを施す方法、円筒形チツ
ブハの端面に金属製キャップを嵌着する方法、セラミッ
クチップ片は電気メッキを亡接施すことはできないから
、これに無電解メッキを行ってこれにハンダメッキを施
して電極を形成する方法などがあった。
(Prior art) Conventionally, when forming electrodes of chip resistors, for example, a paste made of silver and palladium or a paste of silver and glass was applied to the electrode formation portion of the end face of each chip piece. There is a method in which a metal cap is fitted onto the end face of a cylindrical chip.Since electroplating cannot be applied to a ceramic chip piece, electroless plating is applied to it. There was a method of forming electrodes by applying solder plating.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

上述の方法において銀を用いたベニストを塗布する方法
は次のような問題がある。銀が溶融ハンダに対して合金
になり易いのでいわゆるくわれ現象を起して端子の接着
強度を低下させる。銀やパラジウムは8価でありコスト
高になる。焼成には800℃以上の高温焼成が必要であ
るので抵抗皮膜の材質が制限され、ノコ−ボン皮膜抵抗
、金属皮膜抵抗などは使用できない。次に金属キャラ/
を嵌着する方法は、チップ片が小型であるから嵌合精度
の面で技術的に難しくまた手間がかかり生産スピードが
υ1限され、又歩留りが悪くなるという問題がある。次
に無電、vf?メッキのみによる方法は、セラミックと
メッキ皮膜の接着強度が前述の2者に比べて1(り実用
性が低いとい′う問題がある。
In the above-mentioned method, the method of coating Benist using silver has the following problems. Since silver tends to form an alloy with molten solder, a so-called sagging phenomenon occurs, reducing the adhesive strength of the terminal. Silver and palladium are octavalent and therefore expensive. Since high temperature firing of 800° C. or higher is required for firing, the material of the resistive film is limited, and nocobon film resistors, metal film resistors, etc. cannot be used. Next is the metal character/
Since the chip pieces are small, this method is technically difficult and time-consuming in terms of fitting accuracy, which limits the production speed by υ1, and also reduces yield. Next is no electricity, VF? The method using only plating has a problem in that the adhesive strength between the ceramic and the plating film is 1 (1) and less practical than the above-mentioned two methods.

本発明は上述の問題を解決するために、高価な1!ウパ
ラジウムを用いず安価な材料を用い、また同時に銀によ
るはんだくわれの問題を解決し、さらに電に1を1関1
個に嵌るしたり、1個1個にベース1−をj? Tli
するという手数を省き生産性を向上さUようとするもの
である。
In order to solve the above-mentioned problems, the present invention aims to solve the above-mentioned problems by using an expensive 1! It uses inexpensive materials without using upalladium, and at the same time solves the problem of solder creases caused by silver.
Does it fit in each piece or base 1- on each piece? Tli
The aim is to improve productivity by eliminating the hassle of doing so.

(問題点を解決丈るための手段) 本発明は、メタルグレーズよりなる抵抗皮膜で液留され
たチップ状ヒラミック基体のメタルグレーズの一部と、
基体端面のセラミック面とよりなる電極形成部に、弗酸
処理によるエツチング面、ニッケルP m解メッキ層、
銅電気メッキ層、ニッケル電気メッキ層を順次形成し、
弗酸処理によりメタルグレーズ表面のガラス質並にセラ
ミック面の焼成によって生じたガラス質を溶解してエツ
チング面とし無電解メッキによるニッケルの結合性を高
め、次に銅電気メッキ層とニッケル′電気メッキ層を順
次形成することにより、ニッケル無電解メッキ層の厚さ
と強度の不足を補い、かつ9;IA重気気メッキ層より
ニッケル電気メツ4と次の′−1′田メッキの電着の均
一性をはかり、さらに無電解メッキと電気メッキにより
一時に大口を処理し、微少なチップ状基体を1個1個処
理する手数を省き生産性を向上させようとするものであ
る。
(Means for solving the problems) The present invention provides a part of the metal glaze of a chip-shaped helical base, which is liquid-distilled with a resistive film made of metal glaze,
The electrode forming portion consisting of the ceramic surface of the end surface of the base is provided with an etched surface by hydrofluoric acid treatment, a nickel P-plating layer,
Sequentially form a copper electroplating layer and a nickel electroplating layer,
Hydrofluoric acid treatment dissolves the glass on the metal glaze surface as well as the glass generated by firing the ceramic surface, making it an etched surface and increasing the bonding of nickel through electroless plating, followed by copper electroplating and nickel electroplating. By forming the layers sequentially, the lack of thickness and strength of the nickel electroless plating layer is compensated for, and the electrodeposition of the nickel electroplating layer 4 and the next '-1' field plating is more uniform than the IA heavy air plating layer. In addition, by processing a large amount at once using electroless plating and electroplating, it is possible to improve productivity by eliminating the trouble of processing microscopic chip-shaped substrates one by one.

〔作用〕[Effect]

本発明は、メタルグレーズよりなる低抗皮19で被覆し
たチップ状ヒラミック基体の電極形成部に弗酸処理によ
るエツチング面を形成してメタルグレーズのガラス買並
に焼成により析出したセラミック表面のガラス質をとか
し、次にニッケル無電解メッキ層を形成してメタルグレ
ーズ並にセラミックにニッケルを結合させ、次に銅電気
メッキβ、ニッケル電気メッキ層よりニッケル無電解メ
ッキ層に不足する厚さと強度を出し、かつ銅電気メッキ
層はニッケルおよびハンダの電ηを均一にするものであ
る。
In the present invention, an etched surface is formed by hydrofluoric acid treatment on the electrode forming part of a chip-shaped helical base coated with a low-resistance coating 19 made of a metal glaze, and the vitreous quality of the ceramic surface deposited by firing is obtained by forming an etched surface by hydrofluoric acid treatment. Next, a nickel electroless plating layer is formed to bond nickel to the ceramic as well as a metal glaze, and then copper electroplating β is performed to achieve the thickness and strength that the nickel electroless plating layer lacks compared to the nickel electroplating layer. , and the copper electroplating layer makes the electrical η of the nickel and solder uniform.

実/lI例1 円筒形チップ状電子部品の114成の−・例を第1図な
いし第7図に承り製迄工程図によって説明りる。
Actual Example 1 An example of 114 formations of a cylindrical chip-shaped electronic component will be explained with reference to manufacturing process diagrams shown in FIGS. 1 to 7.

(1)  円筒形チップ状セラミック基体1の表面に両
端面を除いて、ガラスに銀とパラジウムを配合したメタ
ルグレーズよりなる抵抗皮膜2を形成する。(第1図は
縦断側面図を示す。以下同様)(2)  抵抗皮膜2の
表面に、両端部を残して耐熱エボシキ塗料よりなる抵抗
保護膜3を形成する。
(1) A resistive film 2 made of a metal glaze made of glass mixed with silver and palladium is formed on the surface of the cylindrical chip-shaped ceramic substrate 1 except for both end faces. (FIG. 1 shows a longitudinal side view. The same applies hereafter.) (2) A resistive protective film 3 made of heat-resistant epoxy paint is formed on the surface of the resistive film 2, leaving both ends intact.

(第2図) (3)  保護膜3の表面を合成樹脂マスキング膜4で
被覆する。(第3図) (4)  全体を弗Fit処理するとマスキングl!1
14の両端に露出したメタルグレーズ面及び基体1の両
端セラミック面のガラス質がとけて除去され、マスキン
グ膜4で被覆されていないメタルグレーズ面とセラミッ
ク面とよりなる電極形成部50表面がエツチング面6と
なり後工程の、I!!!電解メッキによるニッケルとの
結合力が強くなる。(第4図)(5)  エツチング面
6となった電極形成部5に塩化パラジウム処理による活
性化面7を形成し、無電解メッキ金屈が剛着し易い状態
にする。(9〕5図) (6)  保設置I!i!3上のマスキングIts!4
を溶剤等で除去する。(第6図) (7)  全体をニッケル無電解メッキ液に浸漬して無
電解メッキを施し、活性化されlこ電(4形成部5に厚
さ1声〜3虜のニッケル無電解メツ1層8を形成する。
(FIG. 2) (3) Cover the surface of the protective film 3 with a synthetic resin masking film 4. (Figure 3) (4) Masking is done when the whole is processed with FFit! 1
The metal glaze surfaces exposed at both ends of the substrate 14 and the glassy surfaces of the ceramic surfaces at both ends of the substrate 1 are melted and removed, and the surface of the electrode forming portion 50 consisting of the metal glaze surface and the ceramic surface that is not covered with the masking film 4 becomes an etched surface. 6 and the subsequent process, I! ! ! The bonding force with nickel is strengthened by electrolytic plating. (FIG. 4) (5) An activated surface 7 is formed by palladium chloride treatment on the electrode forming portion 5, which has become the etched surface 6, so that the electroless plating metal is easily adhered. (9] Figure 5) (6) Maintenance installation I! i! Its masking on 3! 4
Remove with solvent etc. (Fig. 6) (7) The entire body is immersed in a nickel electroless plating solution to perform electroless plating, and the nickel electroless plating is activated and the nickel electroless metal plate 1 to 3 thick is applied to the 4-forming portion 5. Form layer 8.

り8)  次に銅の電気メッキ浴に浸漬して銅の電気メ
ッキを施し、ニッケル無電解メッキ層8上に厚さ 0.
27m〜0.47gの銅電気メッキ層9を形成づる。
8) Next, electroplating of copper is performed by dipping in a copper electroplating bath, and the electroless nickel plating layer 8 is coated with a thickness of 0.
A copper electroplating layer 9 of 27 m to 0.47 g is formed.

(9)  次にニッケルの電気メッキ浴に浸漬してニッ
ケルの電気メッキを施し、銅電気メツ−1底9上に厚さ
2廊〜5mのニッケルTi気メツー1層10を形成する
。ニッケル電気メッキ層10の〃さがこの片段であれば
、いわゆるはんだくわれの現象を阻止できる。
(9) Next, it is immersed in a nickel electroplating bath to perform nickel electroplating to form a nickel-Ti gas layer 10 having a thickness of 2 to 5 m on the bottom 9 of the copper electroplating layer 1. If the thickness of the nickel electroplated layer 10 is this single step, the phenomenon of so-called solder hollow can be prevented.

(10)  次にハンダメッキ浴中でハンダの電気メッ
キを施し、ニッケル°電気メッキ層10上にP2さ5 
gtn〜10淵のハン//電気メツV層11を形成する
(10) Next, apply solder electroplating in a solder plating bath, and apply P25 on the nickel electroplated layer 10.
An electric mesh V layer 11 of gtn~10 depths is formed.

(第7図) 以1のようにして両端に電lA15aをhillる円筒
形Lンブ払の電子部品△か1°1られる。
(Fig. 7) As described in 1 below, a cylindrical L-shaped electronic component △ or 1°1 is mounted with electric current 15a on both ends.

ニッケル無電解メッキ層8上に銅電気メッキ層94丘し
てニッケル゛市気メツ%−眉i 10を形成することに
3、りニア/ノル無電解メツ)層8甲独ではメツ1の馬
7さど強1αが不足するのを銅電気メツ1層9、ニソウ
ル電気メン1層10を形成してVさと強度をjl−I 
’)さl!る。
The copper electroplating layer 94 is formed on the nickel electroless plating layer 8 to form a nickel layer of 10. To overcome the lack of 7sado strength 1α, form one layer of copper electric metal 9 and one layer of Nisoul electric metal 10 to increase the V and strength to jl-I.
') Sa l! Ru.

さらに、ニッケル、焦電VI?メツ1層8上に直18二
7ノノル1L気メツ1fiioを形成4るとニッケル電
気メン1層10の電?1が不均一になり、また銅電気メ
・t 1層9を省くと、ハンダ電気メツI!yi11の
電着し小鈎−なるため、中間に薄い銅電気メッキ層9べ
rr (rさUるしのである。
Furthermore, nickel, pyroelectric VI? Directly form 18,27, 1L, 1fiio on 1st layer 8 of nickel electricity and 1st layer of 10th layer of nickel electricity? 1 becomes non-uniform, and if you omit the copper electric metal layer 9, the solder electric metal I! In order to form a small hook by electrodepositing YI11, there is a thin copper electroplated layer 9 in the middle.

実施(−112 角形LツI状素子の構成を第8図ないし第17図に示す
装)告工程図によって説明する。
The structure of the (-112) rectangular L-shaped element will be explained with reference to the process diagrams shown in FIGS. 8 to 17.

(1)  多数の角形チップ状ヒラミック基体1の集合
体である平板状のセラミック’Jl&1aの表面に適当
間隔で実施例1と同じ材料よりtiるメタルグレーズ抵
抗皮股2を各ブツブ状廿うミック早体1一個毎にその長
さ方向の全長に形成する。(平面図を第8図に示す) (2)  各抵抗皮膜2の表面に、その長さ1ノ向の両
端部を残して耐熱エポキシ塗料よりなるllt抗保5膜
3を形成する。(平面図を第9図に承り)(3)  保
護膜3の表面並に基体10裏面を合成1j・1脂マスキ
ング1!J4,4aで波音りる。大面のマスキング1J
4aは各基14i1 fQにその長さ方向の両端部を僅
かに残しておく。(裏面からの平面図を第10図、第1
0図のへ−Al17i面を第11図に示づ−)(4) 
 セラミック基板1aを第10図において縦IJ向に分
割し、多数の細長片1bとりる。(平面図4第12図に
承り) (5)  細長片1bに実施例1と同様の弗酸処理を施
し、同様に水洗、乾燥して、マスキング1lQ4,4a
より°露出したメタルグレーズ面性にセラミック面にエ
ツチング面6を形成して電極形成部5を形成する。(1
0艮片の巾方向断面図を第13図に示す)(6)  細
長片1bのエツチング面6となった7tNI形成部5に
実施V141と同様に塩化パラジウム処理を施して活竹
化面7を形成する。<m長片の中方向断面図を第14図
に示1) (7)  マスキング膜4,4aを溶剤で溶解除去する
(1) Metal glaze resistor skins 2 made of the same material as in Example 1 are arranged at appropriate intervals on the surface of a flat ceramic 'Jl&1a' which is an assembly of a large number of square chip-like heramic substrates 1. Form the entire length of each early body in the longitudinal direction. (The plan view is shown in FIG. 8) (2) On the surface of each resistive film 2, an llt anti-resistance film 3 made of heat-resistant epoxy paint is formed, leaving both ends in one direction along its length. (The plan view is shown in FIG. 9) (3) Synthesis of the surface of the protective film 3 and the back surface of the base 10 1j.1 fat masking 1! Nami Riruru on J4, 4a. Large masking 1J
4a leaves a small portion of both ends in the length direction in each group 14i1 fQ. (The plan view from the back is shown in Figure 10 and Figure 1.
Figure 0 shows the Al17i surface in Figure 11) (4)
The ceramic substrate 1a is vertically divided in the IJ direction in FIG. 10 to obtain a large number of strips 1b. (According to plan view 4, Figure 12) (5) The strip 1b is treated with hydrofluoric acid in the same manner as in Example 1, washed with water and dried in the same manner, and masked 1lQ4, 4a.
An etched surface 6 is formed on the ceramic surface on the more exposed surface of the metal glaze to form an electrode forming portion 5. (1
(6) The 7tNI formed portion 5, which became the etched surface 6 of the strip 1b, was treated with palladium chloride in the same manner as in implementation V141 to form the activated bamboo surface 7. Form. <A cross-sectional view in the middle direction of the m-long piece is shown in FIG. 14 1) (7) Masking films 4 and 4a are dissolved and removed using a solvent.

(平面図を第15図に示す) (+1)  ’iIJ V 片1bヲ各基体1FrJp
、:チノブ状に分;1.11 する。(平面図を第16
図に示り゛) (9)  分υ1された角形チップ状セラミック基体1
の粘性化されたi+形成部5に、実M例1と同様に、ニ
ッケル無電解メツ4、銅電気メッキ、ニッケル゛山気メ
ツ1−、ハンダ電気メツVを順次施してニッケル無電解
メッキ層8、銅電気メッキ層9、ニッケル電気メッキ層
10、ハンダ電気メッキ層11を形成する。(拡大縦断
側面図を第17図に示す)以1のようにして両端に電極
5a@(1りる角チップ状市了部品Δ′が1qられる。
(The plan view is shown in Fig. 15) (+1) 'iIJ V Piece 1b, each base 1FrJp
, 1.11 min. (The plan view is 16th
As shown in the figure) (9) Square chip-shaped ceramic substrate 1 divided by υ1
As in Example 1, nickel electroless plating 4, copper electroplating, nickel "mountain plating 1-", and solder electroplating V are sequentially applied to the viscous i+ forming part 5 to form a nickel electroless plating layer. 8. Forming a copper electroplating layer 9, a nickel electroplating layer 10, and a solder electroplating layer 11. (An enlarged vertical side view is shown in FIG. 17.) As described in 1 below, the electrodes 5a@(1q) square chip-shaped finished parts Δ' are provided at both ends.

(R明の効果〕 本発明によれば、チップ状ヒラミック基体に形成された
メタルグレーズよりなる抵抗皮膜をこの両端部を残して
抵抗保護膜で波でし、この抵抗保護膜で被7されない抵
抗皮膜のメタルグレーズ面と基体両端面のセラミック面
とよりなる電1〜形成部に弗酸処理によるエツチング面
を形成し、このエツチング面が形成されたSt+形成部
に順次ニッケル無電解メッキ層、銅電気メッキ層、ニッ
ケル電気メッキ層を順次形成したため、セラミック1.
(体に形成され)ごガラス質よりなる沿らかな抵抗皮膜
性に基体の端面のセラミック面を弗酸処理によりエツチ
ング面にし、このエツチング面によ−)で次の無電解メ
ッキに際して金属ニッケルのU;合を8易にづることが
できる。またイン電性の低い抵抗皮膜性にセラミック面
に無電解メッキを施ηことにより金属ニッケルを結合さ
せたから青電1′1が「1・1句され次の電気メッキを
可能にりることができる。
(Effect of R-light) According to the present invention, a resistive film made of metal glaze formed on a chip-shaped helical base is corrugated with a resistive protective film, leaving both ends of the resistive film, and the resistive film is not covered with the resistive protective film. An etched surface is formed by hydrofluoric acid treatment on the electrode 1~ formation area, which consists of the metal glaze surface of the film and the ceramic surfaces on both end faces of the substrate, and a nickel electroless plating layer and a copper electroless plating layer are sequentially applied to the St+ formation area where this etched surface is formed. Since the electroplating layer and the nickel electroplating layer were sequentially formed, ceramic 1.
The ceramic surface of the edge of the substrate is treated with hydrofluoric acid to form a smooth resistive film made of glass (formed on the body). The combination U can be easily written as 8. In addition, by applying electroless plating to the ceramic surface with a low electrical resistance film, metal nickel was bonded, so Seiden 1'1 was ``1.1'' and the next electroplating was possible. can.

またニッケル無電解メッキ層は剥阿1し易く、表面の弾
痕ム低いが、次の銅電気メッキF′j、ニッケル電気メ
ン1層によってメッキ層に厚さと強度を・保持さけるこ
とができる。さらに銅電気メツ1:層のn /Jに、ノ
リ次の一ツケル電気メツt x−’i 、さらに1よニ
ツ′ノル電気メツ1層」−に形成されるハンダ電気メツ
1一層の°市?Sを均一にりることができる。
Further, although the nickel electroless plating layer is easy to peel off and the bullet holes on the surface are low, the thickness and strength of the plating layer can be maintained by the following copper electroplating F'j and one layer of nickel electroplating. Furthermore, copper metallurgical metal 1: n / J of the layer, one layer of solder electric metal t ? S can be distributed uniformly.

、L /5、rs +v +イf”l トシテ高1i1
1+ <i g rv ハンダ’/ ムラ用いないIこ
め+A $1が′々1lIllであり、銀を用いないた
めはんたく4つれの現家が発1するおそれもない。
, L /5, rs +v +if”l Toshite High 1i1
1+ <i grv solder'/ I solder without unevenness + A $1 is 1lIll, and since no silver is used, there is no risk of the four solders' current homes being sold.

(実験例) 実廁例1のfJ法で1r7られ1.:電(〜ど比較例と
して、−ツケル照電解メツ4一層上にl′l18ハンタ
メッを層を形11にシた電極どの1811強lを比較1
Jる実験を行つ Iこ 。
(Experimental example) Using the fJ method of practical example 1, 1r7 and 1. : As a comparative example, compare the 1811 strength of the electrode with 11 layers of 18 hantamet on top of 4 layers of 1811
I'm going to do an experiment.

試111 :直171.0m1n、長さ2 mmで両端
にニッケル乗1電解メッキ層、このニッケル、?!!電
解電解メツ−1上 た電極を右し、この゛電極の軸方向に首径0、5m.の
リード線をハンダで接続したチップ抵抗器。
Test 111: 171.0m1n in diameter, 2mm in length, electrolytic plating layer of 1 nickel to the power of nickel on both ends, this nickel? ! ! Electrolytic Electrolyte - 1 Place the upper electrode on the right side, and set the neck diameter of 0.5 m in the axial direction of the electrode. A chip resistor whose lead wires are connected with solder.

試.1.i+ 2 :試Fllと同形で両端にニッケル
無電解メッキ層(2m)、銅電気メッキ層(0.3、朋
)、ニッケル電気メッキ層(3−)、ハンダ電気メッキ
層(7沸)の順に形成した電極を1し試R 1と同様に
リード線を接続したチップ抵抗器。
Try. 1. i+ 2: Same shape as test Fll, with nickel electroless plating layer (2m), copper electroplating layer (0.3m), nickel electroplating layer (3-), solder electroplating layer (7m) on both ends in this order. Test R A chip resistor with the formed electrodes connected to lead wires in the same way as in 1.

実験の方法 リード線と把持して軸方向に引張力(壬さ)を加え、電
(唄が剥離するまでの型口を測定した。
Experimental method: We gripped the lead wire and applied a tensile force in the axial direction, and measured the length of the mold until it peeled off.

実験の結果 第18図に示すように試料1はI Kg以下で雷(七が
剥離したが、本発明にJ、る試fl 2 t,1 4 
Kg以FCも電極が剥離ヒず6 8g以上ではリード線
が切断して測定不能になったが強度が大r1Jに+A+
上づることがわかった。
As a result of the experiment, as shown in Fig. 18, sample 1 was damaged by lightning under I Kg (7 parts were peeled off, but the present invention was not tested).
FC below Kg also caused the electrode to peel off. At over 8g, the lead wire broke and measurement became impossible, but the strength increased to r1J +A+
I found out that it goes up.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図ないし第7図は、本発明品の一実施例を示す円筒
形のチップ状電子部品のツJ逍工程図、第8図ないし第
17図は他の実施例を示す角形のチップ状電子部品の製
造工程図、118図+.1本発明による製品と比較例と
の引張強度を示を図表である。 1・・基体、2・・抵抗皮膜、3・・保と膜、5・・電
(ル形成部、6・・エツチング面、8・ニッケル(1(
(電VRメット層、9・・銅電気メッキ層、10・・ニ
ッケル電気メッキ層。 昭和59年10月26日
1 to 7 are manufacturing process diagrams for a cylindrical chip-shaped electronic component showing one embodiment of the present invention, and FIGS. 8 to 17 are angular chip-shaped electronic components showing other embodiments. Manufacturing process diagram for electronic parts, 118 figures +. 1 is a chart showing the tensile strength of a product according to the present invention and a comparative example. 1. Substrate, 2. Resistive film, 3. Preservative film, 5. Electrode (hole forming part), 6. Etched surface, 8. Nickel (1 (
(Electronic VRmet layer, 9. Copper electroplating layer, 10. Nickel electroplating layer. October 26, 1981.

Claims (1)

【特許請求の範囲】[Claims] (1)チップ状セラミック基体にメタルグレーズ抵抗皮
膜を形成し、この抵抗皮膜の両端部を残して中央部に抵
抗保護膜を形成し、前記基体の両端セラミック面と前記
保護膜で被覆されない抵抗皮膜のメタルグレーズ面とよ
りなる電極形成部に弗酸処理によるエッチング面を形成
しこのエッチング面が形成された電極形成部にニッケル
無電解メッキ層、銅電気メッキ層、ニッケル電気メッキ
層を順次形成したことを特徴とするチップ状電子部品。
(1) Form a metal glaze resistance film on a chip-shaped ceramic substrate, leave both ends of this resistance film and form a resistance protection film in the center, and cover the ceramic surfaces of both ends of the substrate and the resistance film not covered with the protection film. An etched surface was formed by hydrofluoric acid treatment on the electrode forming part consisting of the metal glaze surface, and a nickel electroless plating layer, a copper electroplating layer, and a nickel electroplating layer were sequentially formed on the electrode forming part where this etched surface was formed. A chip-shaped electronic component characterized by:
JP59225475A 1984-10-26 1984-10-26 Chip-shaped electronic component Pending JPS61102702A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP59225475A JPS61102702A (en) 1984-10-26 1984-10-26 Chip-shaped electronic component

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59225475A JPS61102702A (en) 1984-10-26 1984-10-26 Chip-shaped electronic component

Publications (1)

Publication Number Publication Date
JPS61102702A true JPS61102702A (en) 1986-05-21

Family

ID=16829895

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59225475A Pending JPS61102702A (en) 1984-10-26 1984-10-26 Chip-shaped electronic component

Country Status (1)

Country Link
JP (1) JPS61102702A (en)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS54157296A (en) * 1978-06-02 1979-12-12 Tdk Corp Electrode structure and the manufacturing method
JPS58107606A (en) * 1981-12-21 1983-06-27 松下電器産業株式会社 Manufacturing method of chip resistor

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS54157296A (en) * 1978-06-02 1979-12-12 Tdk Corp Electrode structure and the manufacturing method
JPS58107606A (en) * 1981-12-21 1983-06-27 松下電器産業株式会社 Manufacturing method of chip resistor

Similar Documents

Publication Publication Date Title
US2734150A (en) Circuit component and method of making same
CN108550451A (en) The manufacturing method of small size film precision resister device
JPS61102702A (en) Chip-shaped electronic component
DE2615473B2 (en) Measuring resistor for a resistance thermometer
JP3118509B2 (en) Chip resistor
JPH0448571A (en) Planar heating element and temperature sensor using hollow insulation substrate
JP2641530B2 (en) Manufacturing method of chip-shaped electronic component
JPS61102703A (en) Chip-shaped electronic component
JPH04329616A (en) Laminated type electronic component
JPS61193303A (en) Chip-shaped electronic component
JPS6019680B2 (en) How to solder to an insulation board
JPH07297006A (en) Chip-shaped electronic component
JPH08124708A (en) Chip-shaped electronic component and manufacturing method thereof
JP2734184B2 (en) TAB tape carrier
JPS5961116A (en) Method of producing chip type solid electrolytic condenser
JPS5858717A (en) Electronic part
JP2537182B2 (en) Method for manufacturing chip-type solid electrolytic capacitor
JPS61193304A (en) Chip-shaped electronic component
DE1465736C (en) Function block. especially for data processing systems
JPH02137280A (en) Electrostrictive effect element and its manufacturing method
JPH05129105A (en) Chip varistor
SU443120A1 (en) A method of making a conductive coating
JPS6199319A (en) Ceramic electronic component
JP2780427B2 (en) TAB tape carrier and method of manufacturing the same
JPS59167094A (en) Method of producing circuit board