JPS61102781A - Method of manufacturing field effect transistor - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a method for manufacturing a field effect transistor suitable for manufacturing an insulated gate field effect transistor (hereinafter referred to as MIS transistor) having a short gate length.

Conventional Technology MIS) transistors, represented by MOS) transistors, are the main components of large-scale integrated circuits (LSI).
In efforts to increase the degree of integration of LSIs, the trend is toward miniaturization. i7j, MIS) The method for manufacturing transistors also uses a flat melting point material such as polycrystalline silicon as the gate electrode, instead of the non-self-aligned method using aluminum as the gate electrode, and uses this gate electrode as a mask to form the drain and source regions. Self-alignment methods have become mainstream.

By the way, with the miniaturization of MIS transistors, a gate length of 1 μm and 8 degrees is required.
Even the self-alignment method described above cannot deal with this problem.

In other words, the reduction in the effective channel length due to lateral diffusion of the drain and source regions cannot be ignored, so it is necessary to form a diffusion layer that will become the drain and source regions as a structure that can eliminate such lateral diffusion. After that, a structure in which this diffusion layer is divided into two by 1% is provided, and a gate electrode is formed inside this layer to form an IT channel region at the bottom of the layer. (For example, Japanese Patent Publication No. 52-23230) Problems to be Solved by the Invention According to the conventional structure, diffusion regions for the drain and source regions are formed before forming the gate electric current.
During the lateral diffusion directly under the gate electrode, dV′i does not occur, however, to obtain this structure, as described above,
Formation of the diffusion region would precede formation of the trench. The degree of control of the depth of this groove is lower than the control accuracy of the diffusion depth. Therefore, it is not easy to make the bottom surface of the groove, which has low control accuracy, coincide with the @ plane of the diffusion region, and it is difficult to control the diffusion depth. A problem arises in that the area is not reliably divided, and the function as a field effect transistor is lost.

Note that in order to eliminate this inconvenience, it is sufficient to make the depth of the groove sufficiently deep, but if Z1°4 is made deep, the width of the groove increases, making it impossible to obtain a short gate length. Furthermore, in the structure in which grooves are formed, step portions are formed at various locations on the semiconductor substrate.

In LSIs, especially those with a high degree of integration, the density of interconnection layers interconnecting many built-in elements is high, and the interconnection layers are arranged avoiding steps on the semiconductor substrate. That's almost impossible.

That is, the interconnection layer extends beyond the step formed on the semiconductor substrate. By the way, although it is desirable that the thickness of the interconnection layer be uniform, there is a tendency for the thickness to become uneven at the stepped portions. Therefore, in the conventional structure, there is a risk that the interconnection layer extending beyond the stepped portion may be disconnected, or even if the interconnection layer is not disconnected, a disconnection accident may occur.

Means for Solving the Problems The method for manufacturing a field effect transistor of the present invention includes forming impurities in the same process as the step of ion-implanting impurities for forming the drain and source regions into the field effect transistor region on the main surface of the semiconductor substrate. The entire ion implantation layer is completely covered, and the drain and source are formed by forming a trench whose depth is equal to or greater than the depth of the diffusion layer after annealing, and by performing an annealing treatment that also serves to activate the impurity ions in the ion implantation layer. The method consists of a step of forming a region, a step of forming a gate insulating film on the inner surface of the trench, and a step of forming a gate electrode on the gate insulating film formed in the same step.

Function: In the method for manufacturing a field effect transistor of the present invention, not only the gate length is uniquely determined by setting the m width, but also the groove forming process 8 is provided between the impurity ion implantation and the annealing process. The annealing process has a high degree of precision in controlling the depth of the trench, thereby determining the relative positional relationship between the bottom of the trench and the front surfaces of the drain and source regions. Furthermore, when forming the gate electrode, the groove can be filled with the gate electrode material to eliminate the stepped portion.

EXAMPLES The manufacturing method of the present invention will be explained in detail below with reference to the drawings.

FIG. 1 is a cross-sectional view showing the structure of a MOS transistor formed by the manufacturing method of the present invention.
A drain region 3 and a source region 4 are formed in this part, and a drain region 3 and a source region 4 are formed in this region.
It has a structure in which a gate oxide film 6 and a polycrystalline silicon gate electrode 6 are formed in the groove.

Next, a manufacturing method for obtaining this structure will be explained with reference to sectional views taken along the manufacturing process in Figure 2.

First, an oxide film 2 having a thickness of approximately 5 mm is selectively formed on a P type/recon substrate 1 using a well-known quick selective polyurethane coating.
Then, during this process, n-type impurity is formed in the entire region where the transistor is formed. After this, for example, an anisotropic dry etching process is performed using a mixed gas of sulfur hexafluoride gas and carbon tetrachloride, and the width is reduced to 1 lt.
8 grooves with a depth of 0.4 μm are formed to partially cover the ion implantation layer 7. Note that a positive type resist mask is used as a mask during this dry etching, but this positive type resist mask can be used later as a mask when forming wiring trenches in the isolation oxide film.

Through the above process, the shape shown in FIG. 1a is obtained.

In addition, in the process of the upper 6 pins, a layer with many crystal defects is formed on the side and bottom surfaces of rRa due to the anisotropic dry etching. This layer is a cause of deterioration of the characteristics of the MOS transistor and should be removed.The inner surface of the groove is enameled by about 11,000 layers with a mixture of filler, glass and water. This etching may be dry etching using 7 Leon gas.Next, although not shown in the drawings, a positive-type mask is used during the dry etching, and then dry etching is performed to a depth of 0 using bfluoropropane gas. A groove for a polycrystalline silicon wiring having a width of 1.6 μm and a width of 1.6 μm is formed in the isolation film. After this, the second
As shown in the figure, a drain region 3 and a source region 4 having a depth of about 0.2 microns are formed. When these regions are formed, diffusion in the groove direction during heat diffusion is blocked by the side surfaces of the groove 8.
Next, one or more treatments are performed to form a nonagate oxide film 6't- to a thickness of about 460 mm using a thermal oxidation method, and then to a thickness of about 0.0 mm by a well-known CVD method over the entire surface of the raw conductor substrate.
A polycrystalline silicon layer 9 having a thickness of 4 μm and a sheet resistance of 15 UaH is deposited, and this is further covered with a bond resist 1o having a thickness of approximately 1.2 μm, as shown in FIG. The surface of the substrate is flattened with a resist. Subsequently, a dry etching process using a mixed gas of chlorine and carbon tetrachloride is carried out to etch back both the resist and the polycrystalline silicon. By the way, the etching rate of both the etching gases is determined to be 1:1, and the polycrystalline silicon remains in such a manner that it completely fills the groove.

By going through the above manufacturing process, the MO shown in Figure 1 can be obtained.
S) A transistor is formed. In this MOS transistor, the bottom portion of the groove is secured as a channel forming region.

Above, the present invention has been explained by exemplifying the method of manufacturing an n-channel type MO8) transistor, but the present invention
OS) It can also be applied to the manufacture of transistors.

Further, it is also possible to use a metal plating material as the gate electrode material, and the resistance of the gate can be reduced. However, in this case, it is necessary to change the composition of the dry etching gas during etchback. In addition, when a structure is adopted in which a wiring groove is formed in the isolation oxide film as in the above practical example, impurities in the channel prevention layer (not shown) under the isolation film may be removed. It is necessary to keep the summer high enough.

Effects of Investigation According to the manufacturing method of the present invention, lateral diffusion during impurity diffusion to form drain and source regions is blocked by the side surfaces of the trench, so the gate length does not become short and the design value is reduced. MIS transistors with various gate lengths can be manufactured.

Therefore, it is possible to fabricate a transistor with a short gate length. In addition, if the etching process tm is such that the etching rate of the electrode material and the mask material is 1:1 compared to the etching of the electrode material when forming the gate electrode, it is possible to flatten the upper part of the groove. This makes it possible to eliminate disconnection problems in interconnection layers. Furthermore, in contrast to a MIS transistor having a short gate length, when manufacturing a transistor with a long gate length, it is possible to extend the gate length beyond the planar dimension by making the trench deeper.

[Brief explanation of the drawing]

FIG. 1 is a cross-sectional view showing the structure of an hQi OS transistor formed by the manufacturing method of the present invention, and FIGS. 2 a to 2 G are cross-sectional views shown along the manufacturing process of the present invention.・・P-type silicon substrate, 2・・・Flame pattern for isolation, 3・・・Drain region, 4・・・・・
- Source region, 5... Gate oxide film, 6...
... Polycrystalline 7 recon gate turtle formation, 7 ... Ion implantation layer, 8 ... Groove, 9 ... Polycrystalline silicon layer, 1o ... Positive shape resist. Name of agent: Patent attorney Toshio Nakao and 1 other person No. 1
Figure 5 Gate Nishiraichi Ml 6

Claims (3)

[Claims] (1) In the field effect transistor region of the main surface of the semiconductor substrate,
A step of ion-injection of impurities for forming drain and source regions, a step of dividing the ion-implanted layer formed in the same step into two and forming a groove with a depth equal to or greater than the depth of the diffusion layer after annealing, and a step of forming a groove in the ion-implanted layer. An annealing process that also activates impurity ions is performed to form drain and source regions, a gate insulating film is formed on the inner surface of the trench, and a gate electrode is formed on the gate insulating film formed in the same process. 1. A method for manufacturing a field effect transistor, comprising a step of forming a field effect transistor. (2) forming the gate electrode comprises depositing a gate electrode material;
2. The method of manufacturing a field effect transistor according to claim 1, wherein the resist film is evenly applied on the upper portion and an etching process is performed in which the etching rate of the resist film is 1:1. (3) In the field effect transistor according to claim 1, the inner surface of the groove is etched by isotropic dry etching between the formation of the groove and the annealing process. Production method.