JPS611038A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS611038A JPS611038A JP59124076A JP12407684A JPS611038A JP S611038 A JPS611038 A JP S611038A JP 59124076 A JP59124076 A JP 59124076A JP 12407684 A JP12407684 A JP 12407684A JP S611038 A JPS611038 A JP S611038A
- Authority
- JP
- Japan
- Prior art keywords
- thin film
- semiconductor element
- semiconductor device
- manufacturing
- semiconductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W20/00—Interconnections in chips, wafers or substrates
- H10W20/01—Manufacture or treatment
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【発明の詳細な説明】
〔発明の技術分野〕
この発明は、半導体装置の製造方法に係り、特に水銀カ
ドミウムテルライド結晶などの非常に脆弱で高価な基材
を用いた半導体素子の電極配線を他の物体の表面上まで
延在させた場合の、半導体素子から他の物体上への電極
配線の形成を容易にした半導体装置の製造方法に関する
ものである。[Detailed Description of the Invention] [Technical Field of the Invention] The present invention relates to a method for manufacturing a semiconductor device, and in particular to a method for manufacturing an electrode wiring of a semiconductor device using a very fragile and expensive base material such as mercury cadmium telluride crystal. The present invention relates to a method for manufacturing a semiconductor device that facilitates the formation of electrode wiring from a semiconductor element to another object when the electrode wiring extends to the surface of the object.
水銀カドミウムテルライド結晶などの非常に脆弱な半導
体基材を用いた半導体素子では電極配線へのボンディン
グを当該素子の上で行うことは困難で、電極配線をボン
ディング可能な部位まで引き出す方式がとられている。In semiconductor devices that use extremely fragile semiconductor substrates such as mercury cadmium telluride crystals, it is difficult to bond to electrode wiring on the device, so a method is used to pull out the electrode wiring to a point where bonding is possible. There is.
従来、この種の装置として第1図、第2図に示すものが
あった。第1図において、(1)は水銀カドミウムテル
ライド結晶などの非常に脆弱で高価な半導体基材を用い
た半導体素子、(2)は電極配線で、この電極配線(2
)を絶縁性基板等の他の部材(3)上にまで延在させた
ものであシ、半導体素子(1)は他の部材(3)の上に
接着剤(4)により固着されたものである。Conventionally, there have been devices of this type as shown in FIGS. 1 and 2. In Figure 1, (1) is a semiconductor element using a very fragile and expensive semiconductor base material such as mercury cadmium telluride crystal, and (2) is an electrode wiring.
) extends onto another member (3) such as an insulating substrate, and the semiconductor element (1) is fixed onto the other member (3) with an adhesive (4). It is.
また、第2図においては、半導体素子(1)と他の部材
(3)とが接着剤(4)によシ同一平面状に結合され、
その上に電極配線(2)が形成されたものである。In addition, in FIG. 2, the semiconductor element (1) and another member (3) are bonded together in the same plane by an adhesive (4),
Electrode wiring (2) is formed thereon.
第1図に示す従来の半導体装置は、写真製版技術を用い
るために、脆弱な水銀カドミウムテルライド結晶からな
る半導体素子(1) k 10〜20Amと薄く研磨し
なければならず、さらに、エツジをエツチング法および
ラッピング法により丸みを持たせる必要があり、このプ
ロセスは大変困難である。In the conventional semiconductor device shown in FIG. 1, in order to use photolithography, the semiconductor element (1) made of a fragile mercury cadmium telluride crystal must be polished to a thin thickness of 10 to 20 Am, and the edges must be etched. This process is very difficult, as it is necessary to create a rounded shape using a rounding method and a lapping method.
また、段差がかなりあるので、写真製版が非常に困難で
あるなどの欠点があった。In addition, since there are considerable steps, photolithography is extremely difficult.
また、第2図に示す従来の半導体装置では、接着剤(4
)の部外をラシビング等の方法により半導体素子(1)
および他の部材(3)と同一平面になるように研磨する
必要があり、プロセス中の工程が著しく困難、かつ、増
大するなどの欠点があった。Furthermore, in the conventional semiconductor device shown in FIG.
) by a method such as lashing.
It is necessary to polish it so that it is flush with the other member (3), which has the disadvantage that the number of steps in the process is extremely difficult and increases.
この発明は以上のような欠点を除去するため罠なされた
もので、半導体素子とその電極配線を延在させるべき絶
縁板などの他の部材とを個々に共通の絶縁性基板に接着
し、半導体素子上面の一部から他の部材上面の一部に薄
膜を架け、その上に写真製版技術を用いて半導体素子お
よび他の部材の両者にまたがる電極配線を形成した後に
上記薄膜を除去することによって、形成が容易で、形成
後は温度変化があっても悪影響を受けることのない電極
配線構造が得られる半導体装置の製造方法を提供するも
のである。This invention was made in order to eliminate the above-mentioned drawbacks, and the semiconductor element and other members such as an insulating plate on which the electrode wiring should be extended are individually adhered to a common insulating substrate, and the semiconductor By extending a thin film from a part of the top surface of the element to a part of the top surface of another member, forming electrode wiring spanning both the semiconductor element and the other member using photolithography technology, and then removing the thin film. The present invention provides a method for manufacturing a semiconductor device that is easy to form and that provides an electrode wiring structure that is not adversely affected by temperature changes after formation.
第3図(a)および(b)はそれぞれこの発明の第1の
実施例方法の中間工程段階での状態を示す側面図および
平面図、第4図(a)および(b)はそれぞれこの第1
の実施例方法によって製造された半導体装置の側面図お
よび平面図である。まず、第3図に示すように、水銀カ
ドミウムテルライド結晶からなる半導体素子(1)と絶
縁板などの他の部材(3)とを互いに間隙をおいて絶縁
性基板(5)の上に150℃以下の低融点半田(6)で
接着固定する。その後に、半導体装置(1)の上表面の
一部と他の部材(3)の上表面の一部との間に上記間隙
の上をまたがって薄膜(7)を載せる。この薄膜(7)
に有機溶剤にある程度の抵抗力をもつネガ形のレジスト
を使用するとよい0この時、薄膜(7)は半導体素子(
1)および他の部材(3)上に密着させる必要があるが
、薄膜(7)にネガ形のレジストを用いるならば、10
0℃前後で約15公租アニールすればよいことが分った
。その後、ノ<ターン形成部分に金などの蒸着およびメ
ッキを行って、その後にエツチング法によってノ(ター
ニングを施して電極配線(2)を形成するO
また、薄膜(7)の形成方法としては、まず、平面度が
±1μm程度の高分子材料でできた薄い板を用意する。FIGS. 3(a) and (b) are a side view and a plan view, respectively, showing the state of the method according to the first embodiment of the present invention at an intermediate process stage, and FIGS. 4(a) and (b) are respectively, 1
FIG. 2 is a side view and a plan view of a semiconductor device manufactured by the example method of FIG. First, as shown in FIG. 3, a semiconductor element (1) made of a mercury cadmium telluride crystal and another member (3) such as an insulating plate are placed on an insulating substrate (5) at 150° C. with a gap between them. Adhesively fix with the following low melting point solder (6). Thereafter, a thin film (7) is placed across the gap between a portion of the upper surface of the semiconductor device (1) and a portion of the upper surface of the other member (3). This thin film (7)
It is advisable to use a negative resist that has a certain degree of resistance to organic solvents. At this time, the thin film (7) is attached to the semiconductor element (
1) and other members (3), but if a negative type resist is used for the thin film (7), 10
It was found that annealing for about 15 minutes at around 0°C was sufficient. Thereafter, the electrode wiring (2) is formed by vapor deposition and plating of gold or the like on the part where the turn is to be formed, and then turning is performed by an etching method to form the electrode wiring (2). First, a thin plate made of a polymeric material with a flatness of approximately ±1 μm is prepared.
その表面にネガレジストを1μm程度の厚みになるよう
に塗布した後、写真製版技術によシ必要な寸法にネガレ
ジストをパターニングした。A negative resist was applied to the surface to a thickness of about 1 μm, and then the negative resist was patterned to the required dimensions by photolithography.
その後、有機溶剤により高分子材料でできた薄い板を溶
かすと、必要とする薄膜(7)を得ることができた。こ
の場合、半導体素子(1)、他の部材(3)のエツジ部
分が少々荒れていても十分プロセスに用いることができ
、第1図に示す従来の構造を持つ場合の接着剤(4)の
研磨工程も必要ない。また、写真製版を行う場合、半導
体素子(1)および他の部材(3)の上面の平面度が問
題になるが、この発明の方法を用いる場合の最大の段差
は薄膜(7)の厚みで約1μmであるので、写真製版技
術を用いることが十分可能であシ、第1図、第2図の従
来構造に比べて大変有利である。Thereafter, by dissolving the thin plate made of polymeric material with an organic solvent, the required thin film (7) could be obtained. In this case, even if the edges of the semiconductor element (1) and other members (3) are slightly rough, they can still be used in the process, and the adhesive (4) with the conventional structure shown in FIG. No polishing process is required. Furthermore, when performing photolithography, the flatness of the upper surfaces of the semiconductor element (1) and other members (3) is a problem, but when using the method of this invention, the maximum step difference is the thickness of the thin film (7). Since the thickness is approximately 1 μm, it is sufficiently possible to use photolithography, which is very advantageous compared to the conventional structure shown in FIGS. 1 and 2.
つづいて、レジストはく離液によって薄膜(7)を除去
することによって、第4図(a) 、 (b)に示す半
導体装置を得る。すなわち、薄膜(7)を残しておくと
、この半導体素子の使用中の温度変化によって、薄膜(
7)と電極配線(2)との熱膨張係数の差にもとづく歪
みが生じ、割れやけがれを発生し、特性劣化をきたすこ
とがあるので、この発明では薄膜(7)を除去した。Subsequently, the thin film (7) is removed using a resist stripper to obtain the semiconductor device shown in FIGS. 4(a) and 4(b). In other words, if the thin film (7) is left, the thin film (7) will be damaged due to temperature changes during use of this semiconductor element.
In this invention, the thin film (7) is removed because distortion may occur due to the difference in thermal expansion coefficient between the electrode wiring (7) and the electrode wiring (2), resulting in cracks and scratches, resulting in deterioration of characteristics.
第5図(a) 、 (b)はそれぞれこの発明の第2の
実施例方法の中間工程段階および完成段階での状態を示
す側面図で、本質的には第1の実施例と同様である。こ
のように写真製版が可能な範囲において、半導体素子(
1)と他の部材(3)との間に段差をもたせてもよい。FIGS. 5(a) and 5(b) are side views showing the intermediate process stage and completion stage of the second embodiment of the method, respectively, and are essentially the same as the first embodiment. . In this way, to the extent that photolithography is possible, semiconductor elements (
A step may be provided between 1) and the other member (3).
第6図(a) 、 (b)はそれぞれこの発明の第3の
実施例方法の中間工程段階および完成段階での状態を示
す側面図で、これも、本質的には第1の実施例と同様で
あり、写真製版が可能な範囲罠おいて厚みをもった薄膜
(7a)を用いてもよい。FIGS. 6(a) and 6(b) are side views showing the intermediate process stage and completion stage, respectively, of the third embodiment of the method of the present invention, which are also essentially the same as the first embodiment. Similarly, a thick thin film (7a) may be used within the range where photolithography is possible.
このように、半導体素子(1)の電極配線を絶縁性基板
等の他の部材(3)上にラッピング工程々しに簡単に延
在させられるようになると、半導体素子(1)の基板が
非常に脆弱なもの、例えば水銀カドミウムテルライド結
晶などのプロセスに大きく寄与する。なぜなら、これら
水銀カドミウムテルライド結晶上にポンディングパッド
を形成すると、ワイヤボンディング時の熱や圧力で水銀
カドミウムテルライド結晶が変質し、それは、直接的に
はポンディングパッドのはがれにつながる。また、ワイ
ヤボンディング時の衝撃は、実際の半導体素子(1)と
しての活性部分に悪影響を与え、ひいてはデバイス性能
の劣化につながる。これらを除くためには、実際の活性
部分とポンディングパッドをある程度離し、また、ポン
ディングパッド面積を非常に大きなものにしなければな
らない。水銀カドミウムテルライド結晶は非常に高価で
あるため、それを少しでも有効活用しようとする点から
みると、ポンディングパッド面積を大きくする上記従来
の解決策は、好ましいものとはいえない。In this way, if the electrode wiring of the semiconductor element (1) can be easily extended onto another member (3) such as an insulating substrate during the lapping process, the substrate of the semiconductor element (1) can be materials that are vulnerable to oxidation, such as mercury-cadmium-telluride crystals. This is because when a bonding pad is formed on these mercury cadmium telluride crystals, the mercury cadmium telluride crystals are altered by the heat and pressure during wire bonding, which directly leads to peeling of the bonding pads. Further, the impact during wire bonding has a negative effect on the active portion of the actual semiconductor element (1), which in turn leads to deterioration of device performance. In order to eliminate these, it is necessary to separate the actual active part and the bonding pad to some extent, and also to make the area of the bonding pad very large. Since mercury cadmium telluride crystals are very expensive, the above-mentioned conventional solution of increasing the area of the bonding pad cannot be said to be preferable from the point of view of trying to utilize it as effectively as possible.
さらに、水銀カドミウムテルライド結晶を用いた半導体
素子(1)は現在、1次元アレイが実用化の段階にある
が、その1次元アレイは、各半導体素子1ごとにワイヤ
ボンディングを行い、他の回路 1に接続している
のが現状である。よって、1次元アレイを製作するとき
、ポンディングパッドの存在は無視できない。このよう
な条件の下で、水銀カドミウムテルライドなどの非常に
脆弱な結晶のプロセスを行うとき、ラッピング工程を全
く必要とせず、他の絶縁性基板上ップの部材(3)上に
ポンディングパッドを形成できるこの発明は、その効果
を十分に発揮するものと思われる。Furthermore, one-dimensional arrays of semiconductor elements (1) using mercury-cadmium-telluride crystals are currently in the stage of practical use, but the one-dimensional arrays require wire bonding for each semiconductor element (1) and other circuits (1). Currently, it is connected to. Therefore, when fabricating a one-dimensional array, the presence of the bonding pad cannot be ignored. Under such conditions, when processing very brittle crystals such as mercury cadmium telluride, no lapping process is required and the bonding pad is placed on the top member (3) on the other insulating substrate. It is believed that this invention, which can form a , will fully exhibit its effects.
以上説明したように1この発明は、半導体素子と他の部
材とが絶縁性基板上に間隔をおき、かつ、半導体素子と
他の部材との両表面の段差が許容値内だ入るように接着
し、前記両表面の一部間を薄膜で接続するようにしたの
で、写真製版技術を用いて同時に電極配線形成ができる
ので、従来のものに比べてプロセスが非常に簡便になり
、集積度も非常によくなる。また、この種の半導体装置
では、低温に冷して用いることが多いが、その場合従来
の方法では、半導体素子と他の部材との熱膨張係数の違
いにより、半導体素子に亀裂が生じることが頻繁に生じ
たが、この発明の方法によれば、半導体素子と他の部材
とが電極配線のみを介して供給されており、電極配線形
成時の薄膜をも除去したので、半導体素子に亀裂が生じ
ることは全くなく、また電極配線と薄膜との熱膨張係数
の差による支障もない極めて優れた半導体装置が得られ
る0As explained above, (1) the present invention is arranged such that a semiconductor element and other members are spaced apart from each other on an insulating substrate, and are bonded together so that the height difference between the surfaces of the semiconductor element and other members is within an allowable value. However, since parts of both surfaces are connected by a thin film, electrode wiring can be formed at the same time using photolithography technology, making the process much simpler than conventional methods and reducing the degree of integration. It gets much better. Additionally, this type of semiconductor device is often cooled to a low temperature before use, but in that case, conventional methods can cause cracks to occur in the semiconductor element due to the difference in thermal expansion coefficient between the semiconductor element and other components. However, according to the method of the present invention, the semiconductor element and other components are supplied only through the electrode wiring, and the thin film used to form the electrode wiring is also removed, so cracks in the semiconductor element can be prevented. It is possible to obtain an extremely excellent semiconductor device without any problem caused by the difference in thermal expansion coefficient between the electrode wiring and the thin film.
第1図および第2図はそれぞれ従来の半導体装置の第1
および第2の例を示す斜視図、第3図(a)および(b
)はそれぞれこの発明の第コ、の実施例方法の中間工程
段階での状態を示す側面図および平面図、第4図(、)
および(b)はそれぞれこの第1の実施例方法で得られ
た半導体装置を示す側面図および平面図、第5図(a)
および(b)はそれぞれとの帛明の第2の実施例方法の
中間工程段階および完成段階での状態を示す側面図、第
6図(a)および(b)はそれぞれこの発明の第3の実
施例方法の中間工程段階および完成段階での状態を示す
側面図である。
図において、(1)は半導体素子、(2)は電極配線、
(3)は他の部材、(5)は絶縁性基板、(7)+(7
a)は薄膜である。
なお、図中同一符号は同一または相当部分を示す0Figures 1 and 2 show the first diagram of a conventional semiconductor device, respectively.
and a perspective view showing the second example, FIGS. 3(a) and (b)
) are a side view and a plan view respectively showing the state at an intermediate process stage of the method according to the embodiment of this invention, and FIG.
5(b) is a side view and a plan view showing the semiconductor device obtained by the method of this first embodiment, respectively, and FIG. 5(a)
and (b) are side views showing the intermediate process stage and completion stage of the second embodiment of the method, respectively, and FIGS. 6(a) and (b) are respectively the third embodiment of the invention. FIG. 3 is a side view showing the state of the example method at an intermediate process stage and a completion stage. In the figure, (1) is a semiconductor element, (2) is an electrode wiring,
(3) is another member, (5) is an insulating substrate, (7) + (7
a) is a thin film. In addition, the same symbols in the figures indicate the same or corresponding parts.
Claims (4)
延在させた構造の半導体装置を製造するに際して、上記
半導体素子と上記他の部材とを互いに間隙をおいて、そ
れぞれの上表面の段差が許容値内に入るように共通の絶
縁性基板上に接着し、上記両上表面の各一部間に上記間
隙上を通つてまたがる薄膜を設け、上記半導体素子の上
表面と上記他の部材の上表面との間に上記薄膜上を介し
て電極配線を形成した後、上記薄膜を除去することを特
徴とする半導体装置の製造方法。(1) When manufacturing a semiconductor device having a structure in which the electrode wiring of a semiconductor element extends to the surface of another member, the semiconductor element and the other member are separated from each other with a gap between them, and the upper surface of each are bonded to a common insulating substrate so that the height difference is within an allowable value, and a thin film is provided between each part of both of the upper surfaces by passing over the gap, and the upper surface of the semiconductor element and the other surfaces are bonded to each other. A method of manufacturing a semiconductor device, comprising forming an electrode wiring on the thin film between the thin film and the upper surface of the member, and then removing the thin film.
の脆い半導体基材を用いたことを特徴とする特許請求の
範囲第1項記載の半導体装置の製造方法。(2) The method of manufacturing a semiconductor device according to claim 1, wherein the semiconductor element uses a brittle semiconductor base material such as mercury cadmium telluride crystal.
する特許請求の範囲第1項または第2項記載の半導体装
置の製造方法。(3) A method for manufacturing a semiconductor device according to claim 1 or 2, characterized in that a negative resist thin film is used as the thin film.
ネガ形レジスト材を薄く塗布しこのネガ形レジスト材に
所要のパターニングを施した後に、上記高分子薄板のみ
を有機溶剤で溶解させてネガ形レジスト薄膜を得ること
を特徴とする特許請求の範囲第3項記載の半導体装置の
製造方法。(4) As a method for forming a thin film, a thin polymer plate is used, a negative resist material is thinly applied onto it, and the negative resist material is patterned in the desired manner, and then only the polymer thin plate is dissolved with an organic solvent. 4. The method of manufacturing a semiconductor device according to claim 3, wherein a negative resist thin film is obtained.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59124076A JPS611038A (en) | 1984-06-13 | 1984-06-13 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59124076A JPS611038A (en) | 1984-06-13 | 1984-06-13 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS611038A true JPS611038A (en) | 1986-01-07 |
Family
ID=14876335
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP59124076A Pending JPS611038A (en) | 1984-06-13 | 1984-06-13 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS611038A (en) |
-
1984
- 1984-06-13 JP JP59124076A patent/JPS611038A/en active Pending
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