JPS61128331A - Data transfer control system - Google Patents

Abstract

PURPOSE:To update the large part of supervisory processing for receiving data length by a multiple of once and to improve the economical efficiency of a data transfer circuit by setting up the data length to the multiple of buffer length and holding fraction data length less than the buffer length. CONSTITUTION:Data from one device is inputted to a buffer 2 in a data transmission control system through a data line 1 and transmitted to the other device through a data line 3. The data transmission is controlled by an address resister 4, a difference detecting counter 8 and and address register 9. The quantient obtained by dividing an integer by the number of bytes of the buffer 2 is defined as the buffer multiple and the residual is defined as the fraction data length. The buffer multiple is loaded to a memory in a microprocessor 21 and the fraction data length is set up previously in a register 20. A comparator 22 always compares the contents of the registers 4, 20 and the processor 21 is interrupted by a carry signal 24 from the register 4. Thus, the large part of the supervisory processing of the data length is updated by the multiple of once and the operation of the data transfer circuit is simplified.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for controlling data transfer between devices of an information processing system.

In data transfer between two devices, etc., when the data transfer speeds of the two devices do not completely match, a method is often used in which a so-called buffer is provided between the two devices and data is sent and received via the buffer.

Particularly when the data transfer speed is relatively high, a data transfer circuit of this type is usually constructed only of so-called hardware circuits, resulting in a relatively high efficiency circuit.

[Prior Art and Problems to be Solved by the Invention] FIG. 2 is a block diagram showing an example of the configuration of a data transfer circuit that transfers data via a buffer.

Data is input from one device to a buffer 2 via a data line 1, for example, and the data in the buffer 2 is read out to a data line 3 and transferred to the other device.

The address register 4 is configured to hold, for example, the byte address of the buffer 2 as an address value, and the address value is incremented by a +1 circuit 5, and returns to 0 after a maximum count value equal to, for example, the buffer length. .

This address value is sent to buffer 2 on address line 6,
Controls the data write address of buffer 2.

The address register 4 is updated once by enabling the +1 circuit 5 by a signal sent from the data source device to the control line 7 in synchronization with the data on the data line 1.

This signal is also supplied to the difference detection counter 8 and increments the counter by one.

The address register 9 indicates the storage address of the buffer 2 for data to be transferred to the data transfer destination device,
For example, one byte is read from the buffer 2 and transferred according to a request signal on the control line 10 from the data transfer destination device.
Address register 9 is updated to point to the next storage address.

However, the above data transfer and address register 9 updating operations are controlled by the 0 detection circuit 11 and the address register 9 is updated so that they are executed on the condition that the content of the difference detection counter 8 is not 0. At the same time, the difference detection counter 8 is decremented by 1.

In parallel with the above operations, the byte counter 12 monitors the completion of data transfer.

For this purpose, the data length of the transfer data (for example, the number of bytes) is set in the byte counter 12 prior to data transfer, and is decremented by 1 every time one data is received, and the byte counter 12 becomes 0 by the 0 detection circuit 13. When this is detected, the signal on control line 7 is blocked. .

Also, each time the difference detection counter 8 also becomes 0.

End of data transfer is detected.

According to the above configuration, in order to detect the end of data transfer,
Since it is necessary to update the byte counter 12 and detect 0 each time data is received, especially when considering relatively high-speed data transfer, it is necessary to provide the end detection function as a dedicated hardware circuit, and the microprocessor There is a problem in that it cannot be made economical through control.

(Means for solving the problem) The problem described above is that the data is received in a fixed length buffer,
In the device for transferring via the buffer, a register means for holding the data length of the received data divided into a multiple value of the buffer length and a fractional data length value less than the buffer length, and a register means to write the received data. It has an address register that holds an address in the buffer and updates the address for each write, and is configured to detect the end of reception of the data based on the address value, the multiple value, and the fractional data length value. This problem is solved by the data transfer control method of the present invention.

[Effect]

In other words, since the transfer data length is held as a multiple of the buffer length and as a fractional data length (for example, number of bytes) that is less than the buffer length, most of the process of monitoring the received data length is performed every time data for the buffer is received. The above multiple is updated once, and only the last fraction of the transferred data is updated, for example, by 1.
Requires a byte-by-byte comparison.

Therefore, the load on this part is reduced compared to the conventional system, and at least the updating of the multiple value can be controlled by the microprocessor.

In addition, in order to monitor each byte, the register for holding the above-mentioned fraction need only be able to hold the byte value up to the buffer length, so it is generally a shorter register than a conventional byte counter that holds the byte value of the total length of the transferred data. That's fine.

〔Example〕

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention. In FIG. 0, the same parts as in FIG. 2 are denoted by the same reference numerals.

Data transfer control by the address register 4, difference detection counter 8, address register 9, etc. is performed in the same manner as before.

In order to detect the end of data transfer, the transfer data length, which is indicated by the number of bytes, is divided by an integer by the number of bytes in the buffer 2, and the quotient is the buffer multiple, and the remainder is the fractional data length.

The fractional data length is preset in the register 20, and the buffer multiple is preloaded into the memory of the microprocessor 21.

Although the contents of register 20 are constantly compared with the contents of address register 4, the output of comparison circuit 22 is not enabled until latch 23 is turned on.

A carry signal 24 when the address register 4 is incremented to the maximum value and returned to 0 is connected to the microprocessor 21 as an interrupt signal, and therefore the buffer 2
An interrupt is generated to the microprocessor 21 every time data equal to the data length is received.

In response to this interrupt, the microprocessor 21 decrements the buffer multiple value held in the memory by 1, checks whether the updated value is O, and if it is not 0, stores the updated value in the memory and completes one process.

If the buffer multiple value is -l and becomes O, then
The latch 23 is set on, and the match output of the comparison circuit 22 is enabled.

When the address register 4 is incremented by subsequent transfer≠-data reception and matches the fractional data length of the register 20, the signal on the control line 7 is blocked by the match output of the comparison circuit 22. Further, when the difference detection counter 8 becomes O, the end of the transfer is detected.

In the above, a method using one buffer has been described as an example, but it is clear from the above description that a person skilled in the art can easily apply the present invention to a so-called alternating buffer method using two buffers. be.

〔Effect of the invention〕

As is clear from the above description, the present invention has a significant industrial effect of improving the economic efficiency of data transfer circuits.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an embodiment of the present invention, and FIG. 2 is a block diagram of an example of a conventional configuration. In the figure, 2 is a buffer, 4 is an address register, 8 is a difference detection counter, 9 is an address register, 11.13
is a 0 detection circuit, 12 is a byte counter, 20 is a register, 21 is a microprocessor,

Claims (1)

[Claims] In a device that receives data into a fixed-length buffer and transfers it via the buffer, the data length of the received data is divided into a multiple value of the buffer length and a fractional data length value less than the buffer length and held. register means and holding an address within the buffer to which the received data is to be written;
The data transfer is characterized in that it has an address register that updates the address each time the write is performed, and is configured to detect the end of reception of the data based on the address value, the multiple value, and the fractional data length value. control method.