JPS6113937U - 半導体装置 - Google Patents

半導体装置

Info

Publication number
JPS6113937U
JPS6113937U JP1984097505U JP9750584U JPS6113937U JP S6113937 U JPS6113937 U JP S6113937U JP 1984097505 U JP1984097505 U JP 1984097505U JP 9750584 U JP9750584 U JP 9750584U JP S6113937 U JPS6113937 U JP S6113937U
Authority
JP
Japan
Prior art keywords
semiconductor equipment
semiconductor element
circuit component
semiconductor
view
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1984097505U
Other languages
English (en)
Inventor
朗 佐藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP1984097505U priority Critical patent/JPS6113937U/ja
Publication of JPS6113937U publication Critical patent/JPS6113937U/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/30—Die-attach connectors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H10W72/013—Manufacture or treatment of die-attach connectors
    • H10W72/01308—Manufacture or treatment of die-attach connectors using permanent auxiliary members, e.g. using alignment marks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/073—Connecting or disconnecting of die-attach connectors
    • H10W72/07311—Treating the bonding area before connecting, e.g. by applying flux or cleaning
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/541—Dispositions of bond wires
    • H10W72/5445—Dispositions of bond wires being orthogonal to a side surface of the chip, e.g. parallel arrangements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/931—Shapes of bond pads
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/756—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked lead frame, conducting package substrate or heat sink

Landscapes

  • Die Bonding (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。

Description

【図面の簡単な説明】
第１図は、総合利得と接地インダクタンスとの関係を示
すグラフである。 第２図Ａは従来のマイクロ波素子の平面図、同図Ｂはそ
の断面図である。 第３図Ａは本考案の一実施例によるマイクロ波素子の平
面図、同図Ｂはその断面図である。 １，１１・・・・・・ワイヤー、２．１２・・・・・・
マイクロ波半導体素子、３，１３・・・・・一容器基板
、４．１４・・・・・・マイクロ波素子搭載用突起部、
５，１５・・・・・・薄膜基板、６，１６・・・・・・
内部リード、７，１７・・・・・・内部リード、１８・
・・・・・位置決め溝。

Claims (1)

    【実用新案登録請求の範囲】
  1. 半導体素子又は、半導体素子及び回路部品を搭載した半
    導体装置において、前記半導体素子又は、回路部品を搭
    載する面に位置決め用溝を設けたことを特徴とする半導
    体装置。
JP1984097505U 1984-06-28 1984-06-28 半導体装置 Pending JPS6113937U (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1984097505U JPS6113937U (ja) 1984-06-28 1984-06-28 半導体装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1984097505U JPS6113937U (ja) 1984-06-28 1984-06-28 半導体装置

Publications (1)

Publication Number Publication Date
JPS6113937U true JPS6113937U (ja) 1986-01-27

Family

ID=30657061

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1984097505U Pending JPS6113937U (ja) 1984-06-28 1984-06-28 半導体装置

Country Status (1)

Country Link
JP (1) JPS6113937U (ja)

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