JPS61166130A - ホトレジストパタ−ンの形成方法 - Google Patents

ホトレジストパタ−ンの形成方法

Info

Publication number
JPS61166130A
JPS61166130A JP60006964A JP696485A JPS61166130A JP S61166130 A JPS61166130 A JP S61166130A JP 60006964 A JP60006964 A JP 60006964A JP 696485 A JP696485 A JP 696485A JP S61166130 A JPS61166130 A JP S61166130A
Authority
JP
Japan
Prior art keywords
resist
opening
exposed
photoresist
pattern
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP60006964A
Other languages
English (en)
Japanese (ja)
Other versions
JPH058567B2 (2
Inventor
Yoshihiro Todokoro
義博 戸所
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electronics Corp filed Critical Matsushita Electronics Corp
Priority to JP60006964A priority Critical patent/JPS61166130A/ja
Publication of JPS61166130A publication Critical patent/JPS61166130A/ja
Publication of JPH058567B2 publication Critical patent/JPH058567B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P95/00—Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass

Landscapes

  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
  • Photosensitive Polymer And Photoresist Processing (AREA)
  • Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
  • Drying Of Semiconductors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
JP60006964A 1985-01-18 1985-01-18 ホトレジストパタ−ンの形成方法 Granted JPS61166130A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP60006964A JPS61166130A (ja) 1985-01-18 1985-01-18 ホトレジストパタ−ンの形成方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60006964A JPS61166130A (ja) 1985-01-18 1985-01-18 ホトレジストパタ−ンの形成方法

Publications (2)

Publication Number Publication Date
JPS61166130A true JPS61166130A (ja) 1986-07-26
JPH058567B2 JPH058567B2 (2) 1993-02-02

Family

ID=11652888

Family Applications (1)

Application Number Title Priority Date Filing Date
JP60006964A Granted JPS61166130A (ja) 1985-01-18 1985-01-18 ホトレジストパタ−ンの形成方法

Country Status (1)

Country Link
JP (1) JPS61166130A (2)

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63261836A (ja) * 1987-04-20 1988-10-28 Nec Corp 縮小投影露光法によるテ−パ−形成方法
JPS63301521A (ja) * 1987-06-01 1988-12-08 Nec Corp パタ−ン形成法
US5096802A (en) * 1990-11-09 1992-03-17 Hewlett-Packard Company Holes and spaces shrinkage
US5516626A (en) * 1990-04-23 1996-05-14 Tadahiro Ohmi Resist processing method
US6956641B2 (en) 2000-03-27 2005-10-18 Oki Electric Industry, Co., Ltd. Method of forming resist pattern, and exposure device
JP2016511544A (ja) * 2013-02-15 2016-04-14 トランスフォーム インコーポレーテッド 半導体デバイスの電極及びその製造方法
CN106504981A (zh) * 2016-10-14 2017-03-15 电子科技大学 一种制备角度可控缓坡微结构的方法

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63261836A (ja) * 1987-04-20 1988-10-28 Nec Corp 縮小投影露光法によるテ−パ−形成方法
JPS63301521A (ja) * 1987-06-01 1988-12-08 Nec Corp パタ−ン形成法
US5516626A (en) * 1990-04-23 1996-05-14 Tadahiro Ohmi Resist processing method
US5096802A (en) * 1990-11-09 1992-03-17 Hewlett-Packard Company Holes and spaces shrinkage
US6956641B2 (en) 2000-03-27 2005-10-18 Oki Electric Industry, Co., Ltd. Method of forming resist pattern, and exposure device
JP2016511544A (ja) * 2013-02-15 2016-04-14 トランスフォーム インコーポレーテッド 半導体デバイスの電極及びその製造方法
CN106504981A (zh) * 2016-10-14 2017-03-15 电子科技大学 一种制备角度可控缓坡微结构的方法

Also Published As

Publication number Publication date
JPH058567B2 (2) 1993-02-02

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