JPS61168232A - Die-bonding method of semiconductor element - Google Patents

Die-bonding method of semiconductor element

Info

Publication number
JPS61168232A
JPS61168232A JP60007464A JP746485A JPS61168232A JP S61168232 A JPS61168232 A JP S61168232A JP 60007464 A JP60007464 A JP 60007464A JP 746485 A JP746485 A JP 746485A JP S61168232 A JPS61168232 A JP S61168232A
Authority
JP
Japan
Prior art keywords
semiconductor element
photoresist
die
frame
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP60007464A
Other languages
Japanese (ja)
Inventor
Koji Yamakoshi
山越　晃次
Kazuaki Uemura
植村　和昭
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Oki Electric Industry Co Ltd
Original Assignee
Oki Electric Industry Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Oki Electric Industry Co Ltd filed Critical Oki Electric Industry Co Ltd
Priority to JP60007464A priority Critical patent/JPS61168232A/en
Publication of JPS61168232A publication Critical patent/JPS61168232A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/073—Connecting or disconnecting of die-attach connectors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/073—Connecting or disconnecting of die-attach connectors
    • H10W72/07331—Connecting techniques
    • H10W72/07337—Connecting techniques using a polymer adhesive, e.g. an adhesive based on silicone or epoxy
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/734—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked insulating package substrate, interposer or RDL

Landscapes

  • Die Bonding (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【発明の詳細な説明】 （産業上の利用分野） この発明は、ホトプリンタにおけるＬＥＤアレーなと半
導体素子のダイスボンディング方法に関する。DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a die bonding method for semiconductor elements such as LED arrays in photoprinters.

（従来の技術） 従来、半導体素子のダイスボンディングは、Ｓｅｍ１ｃ
ｏｎｄｕｃｔｏｒ　Ｗｏｒｌｄ　（３）　（１９８４）
　Ｐ８２−８７に記載されるように、パターン認識法あ
るいは機械的方法による位置決めに加えて、Ａｕ−８ｔ
の共晶せたは導電性樹脂を用いてスクラブを行うやり方
と、ハンダクリームや接着剤を用いて行うやり方などが
一般的な方法であった。(Prior art) Conventionally, die bonding of semiconductor elements is performed using Sem1c.
onductor World (3) (1984)
As described in P82-87, in addition to positioning by pattern recognition method or mechanical method, Au-8t
Common methods include scrubbing using eutectic or conductive resin, and using solder cream or adhesive.

（発明が解決しようとする問題点） しかるに、上記従来の方法の特にハンダクリームを用い
る方法では、リフロー炉による加熱時（この加熱により
ハンダクリームが溶解する）に半導体素子が動き、位置
決め精度が悪化する欠点があった。(Problems to be Solved by the Invention) However, in the above-mentioned conventional methods, particularly in the method using solder cream, the semiconductor element moves during heating in a reflow oven (the solder cream melts due to this heating), which deteriorates positioning accuracy. There was a drawback.

（問題点を解決するための手段） この発明は上記問題点を解決するため、基板上にホトレ
ジストの枠を作り、その中でハンダクリームを用いて半
導体素子を基板に接合させる。(Means for Solving the Problems) In order to solve the above-mentioned problems, the present invention creates a photoresist frame on a substrate, and within the frame, a semiconductor element is bonded to the substrate using solder cream.

（作用） このようにすると、リフロー炉による加熱時、ホトレジ
ストの枠によシ半導体素子の動きが規制されるので、半
導体素子の位置決め精度が悪化することがなくなる。(Function) In this way, the movement of the semiconductor element is restricted by the photoresist frame during heating in the reflow oven, so that the positioning accuracy of the semiconductor element does not deteriorate.

（実施例） 以下この発明の一実施例を図面を参照して説明する。一
実施例は、ホトプリンタにおけるＬＥＤアレーを基板上
にダイスポンディングする場合である。(Embodiment) An embodiment of the present invention will be described below with reference to the drawings. One example is die-bonding an LED array onto a substrate in a photoprinter.

第１図（ａ）（平面図）および第１図（ｂ）　（（ａ）
のｂ−す線断面図）において、■は、表面にＡｕなどで
電極パターン２を形成した基板であり、まず、この基板
１上にホトレジストを２０〜３０μ厚に塗布し、恒温槽
にてプリベークする。次に、ガラスマスクを用いた露光
、現像さらにはボストベースを前記ホトレジストに対し
て実施することにより、図に示すようにホトレジストの
枠３を形成する。Figure 1(a) (top view) and Figure 1(b) ((a)
In the cross-sectional view taken along the b-line in Figure 1), ■ is a substrate on which an electrode pattern 2 is formed of Au or the like. First, a photoresist is applied to a thickness of 20 to 30 μm on this substrate 1, and then prebaked in a thermostatic oven. do. Next, the photoresist is exposed to light using a glass mask, developed, and then subjected to a boss base to form a frame 3 of the photoresist as shown in the figure.

この時、ホトレジスト枠３は、ＬＥＤアレーの素子数分
だけ、隣接する一辺を共通にして一直線上に形成される
。まだ、枠内部の間隔は、ＬＥＤアレーの素子間間隔と
等しくされる。しかる後、メタルマスクを用いてハンダ
クリーム４を各ホトレジスト枠３内に印刷する。その後
、ピッカーにてＬＥＤアレーの各素子５をホトレジスト
枠３内に並べ、次にリフロー炉にで加熱する。すると、
ハンダクリーム４が溶解し、ＬＥＤアレーの各素子５が
基板１、詳しくは電極パターン２にハンダ接合される。At this time, the photoresist frame 3 is formed in a straight line for the number of elements of the LED array, with adjacent sides being common. Still, the spacing inside the frame is made equal to the inter-element spacing of the LED array. Thereafter, solder cream 4 is printed inside each photoresist frame 3 using a metal mask. Thereafter, each element 5 of the LED array is arranged in a photoresist frame 3 using a picker, and then heated in a reflow oven. Then,
The solder cream 4 is melted, and each element 5 of the LED array is soldered to the substrate 1, specifically the electrode pattern 2.

この時、ＬＥＤアレーの各素子５の動きはホトレジスト
枠３で規制されるので、各素子５の位置がずれることは
なくなる。At this time, since the movement of each element 5 of the LED array is regulated by the photoresist frame 3, the position of each element 5 will not shift.

（発明の効果） 以上のように、この発明の半導体素子のダイスポンディ
ング方法によれば、リフロー炉による加熱時の半導体素
子の動きをホトレジスト枠により規制するようにしたの
で、従来に比較し半導体素子の位置決め精度が向上する
。また、この発明の方法によれば、ホトレジスト枠内に
挿入するだけで半導体素子を高精度に位置決めでき、し
たがって半導体素子の交換も容易になる。(Effects of the Invention) As described above, according to the die-sponding method for a semiconductor element of the present invention, the movement of the semiconductor element during heating in a reflow oven is regulated by the photoresist frame. positioning accuracy is improved. Further, according to the method of the present invention, the semiconductor element can be positioned with high precision simply by inserting it into the photoresist frame, and therefore the semiconductor element can be easily replaced.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図はこの発明の半導体素子のダイスポンディング方
法の一実施例を説明するための図で、（ａ）は平面図、
（ｂ）は断面図である。 １・・・基板、３・・・ホトレジスト枠、４・・・ノー
ンダクリーム、５・・・ＬＥＤアレーの各素子。 １．４祈 ２電亦ｈハ゛ターン ３、片・トしレストオ十 ４：ハングーク゛ルム ５：Ｌ＆ρアＵ−の８素李FIG. 1 is a diagram for explaining an embodiment of the method for die-bonding a semiconductor device according to the present invention, in which (a) is a plan view;
(b) is a sectional view. DESCRIPTION OF SYMBOLS 1...Substrate, 3...Photoresist frame, 4...Non-da cream, 5...Each element of the LED array. 1.4 Prayer 2 Telephone High Turn 3, Kata・Toshi Resto 14: Hangu Column 5: L & ρ A U- 8 Soli

Claims (1)

【特許請求の範囲】[Claims] 基板上にホトレジストを塗布する工程と、そのホトレジ
ストを露光・現像してホトレジスト枠を形成する工程と
、そのホトレジスト枠内にハンダクリームを印刷し、さ
らに半導体素子をホトレジスト枠内に挿入する工程と、
その後リフロー炉でハンダクリームを溶解し、前記半導
体素子を基板上にハンダ接合させる工程とを具備してな
る半導体素子のダイスボンディング方法。a step of applying a photoresist on a substrate, a step of exposing and developing the photoresist to form a photoresist frame, a step of printing solder cream within the photoresist frame, and further a step of inserting a semiconductor element into the photoresist frame;
A method for die bonding a semiconductor element, comprising the steps of: thereafter melting the solder cream in a reflow oven and soldering the semiconductor element onto a substrate.
JP60007464A 1985-01-21 1985-01-21 Die-bonding method of semiconductor element Pending JPS61168232A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP60007464A JPS61168232A (en) 1985-01-21 1985-01-21 Die-bonding method of semiconductor element

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60007464A JPS61168232A (en) 1985-01-21 1985-01-21 Die-bonding method of semiconductor element

Publications (1)

Publication Number Publication Date
JPS61168232A true JPS61168232A (en) 1986-07-29

Family

ID=11666532

Family Applications (1)

Application Number Title Priority Date Filing Date
JP60007464A Pending JPS61168232A (en) 1985-01-21 1985-01-21 Die-bonding method of semiconductor element

Country Status (1)

Country Link
JP (1) JPS61168232A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5125153A (en) * 1989-11-09 1992-06-30 Oerlikon-Contraves Ag Method of making a hybrid electronic array
WO2017122306A1 (en) * 2016-01-14 2017-07-20 三菱電機株式会社 Heatsink structure, semiconductor device, and method for manufacturing heatsink structure

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5125153A (en) * 1989-11-09 1992-06-30 Oerlikon-Contraves Ag Method of making a hybrid electronic array
WO2017122306A1 (en) * 2016-01-14 2017-07-20 三菱電機株式会社 Heatsink structure, semiconductor device, and method for manufacturing heatsink structure
JPWO2017122306A1 (en) * 2016-01-14 2018-04-12 三菱電機株式会社 Heat sink structure, semiconductor device, and method of manufacturing heat sink structure
CN108463879A (en) * 2016-01-14 2018-08-28 三菱电机株式会社 Heat sink structure, semiconductor device, and method for manufacturing heat sink structure
US10692794B2 (en) 2016-01-14 2020-06-23 Mitsubishi Electric Corporation Radiation plate structure, semiconductor device, and method for manufacturing radiation plate structure
DE112016006225B4 (en) 2016-01-14 2022-04-21 Mitsubishi Electric Corporation Semiconductor device and method of manufacturing a semiconductor device having a radiating plate structure

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