JPS61277276A - Digital filter - Google Patents

Abstract

PURPOSE:To simplify the circuit constitution by providing a delay means storing a digital video signal for a time required for simultaneousity and applying signal delay and a coefficient device multiplying a coefficient required for weight means with the digital video signal. CONSTITUTION:The coefficient device 14 multiplies a coefficient 1/4 with an input signal and connects as AD converter 8 and an adder 17. The adder 17 adds the output of the coefficient device 14 and outputs of both line memories 12, 13 and the added output is fed to a DA converter 9. A digital filter 11 multiplies respectively coefficients of 1/4, 1/2, 1/4 with the present signal, the preceding line and the signal before two lines and adds the result, and since image information for 2 lines' content to be interleaved is compensated during the vertical interpolation, the capacity of line memories 12, 13 has a storage capacity by one bit in comparison with that of conventional line memories 2, 3. Thus, the reduced picture applied with vertical interpolation is obtained with simple circuit constitution.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a digital filter suitable for vertical interpolation of reduced images.

[Conventional technology]

The entire screen of the picture tube of the television receiver is used as the main screen,
An image display device is known that can display a sub-screen in part of the image. In this type of image display device, the image information of the child screen that is inserted into the main screen only needs to be composed of horizontal scanning lines equal to the number of horizontal scanning lines of the main image, and the image is compressed by thinning out the horizontal scanning lines. There is. The conventional digital filter shown in Figure 3 is a filter that, when two of the three horizontal scanning lines are thinned out, takes in the video information of the two horizontal scanning lines that have been thinned out by weighting them appropriately. It is a circuit with two line memories 2
, 3, three coefficient multipliers 4, 5° 6, and an adder 7. The video signal converted into a digital signal by the AD converter 8 is as follows.

The current signal multiplied by 7 by the coefficient multiplier 4, the previous signal of one line passed through the line memory 2 and the multiplied multiplier 5,
Furthermore, the signal from the previous two lines which has passed through the lζ line memories 2 and 3 and the coefficient multiplier 6 and has been multiplied by one is simultaneously added by an adder 7 and is supplied to a DA converter 9.

[Problem that the invention seeks to solve]

The above conventional digital filter has line memory 2,
The storage capacity of 3 must correspond to the number of bits of the input video signal, so a large storage capacity is required, and three coefficient books 4, 5.6 are also required, so 1 There were problems such as a complicated circuit configuration.

[Means for solving problems]

This invention solves the above problems.

A delay means for storing and delaying the digital video signals for the horizontal scanning lines thinned out to obtain a reduced image for a time necessary for synchronization, and a q-? The gist of the present invention is to provide a coefficient multiplier for multiplying the weighted average of nl digital video signals by a necessary coefficient.

[Effect]

The present invention uses a digital video signal related to thinned horizontal scanning lines to form a reduced image.

Before being delayed in the storage means, the information is weighted by multiplying it by an appropriate coefficient, and as a result of the weighting by 1, the storage capacity of the storage means is reduced by the amount that the information is compressed.

〔Example〕

Embodiments of the present invention will be described below with reference to FIGS. 41-1 and 2. FIG. 1 is a circuit diagram showing an embodiment of a digital filter of the present invention.

In FIG. 1, a digital filter 1 includes two line memories 12, 13 and three coefficient units 14, 15, 16.
and an adder 17, and a coefficient unit 15
By providing the line memories IJ 12 and 13 at the front stage, respectively, the storage capacity of the line memories 12 and 13 can be reduced. That is, since the first stage line memory is connected to the AD converter 8 via the coefficient multiplier 15 that multiplies the coefficient 1, it is sufficient to have a storage capacity that is 1 bit less than the number of bits of the input video signal.

Furthermore, since the primary stage line memory 3 is connected to the first stage line memory 2 via the coefficient multiplier 16 which multiplies the coefficient 1, the storage capacity may be 1 bit smaller than that of the first stage line memory 2. become.

The coefficient unit 14 multiplies the input signal by a coefficient 1,
It is connected between the AD converter 8 and the adder 17. Adder 17 outputs the output of coefficient unit 14 and both line memo! J12
, 13 outputs are added, and the added output is D
It is supplied to the A converter 9.

In this way, the digital filter 11 filters the current signal and the signals one line and two lines before it.

The video information for two lines, which are multiplied by respective coefficients of 1 and 1.1 and added and thinned out by one, can be supplemented by vertical interpolation, but line memories 12 and 13 are different from conventional line memories 2 and 3. The memory capacity is 1 bit less than that, and an inexpensive circuit configuration is possible.

In the above embodiment, the signal delayed by the first stage line memory 12 is further delayed by the first stage line memory 13, but the digital filter 2 shown in FIG.
1, two line memories 22, 2 are parallel to each other.
This digital filter 21 may be configured to form a signal necessary for vertical interpolation by controlling the write and read timings of 3.This digital filter 21 has one each of coefficients T, 25, and By the way, for the coefficient skill,
A line memo IJ 23 and an adder 27 are connected to each other via a bus control circuit 29, and a coefficient unit 27 is connected thereto.

A line memory 22 is connected via a bus control circuit 30. A bus control circuit 31 is interposed between the line memo IJ 23 and the adder 27.

The read timing of line memory edicts is controlled. The adder n has a path control circuit section and 31
, a latch circuit 33 that latches the output of the adder circuit 32 , and an adder circuit that receives the outputs of both the latch circuit section and the line memory 22 as inputs. Adder circuit A is connected to DA converter 9 via latch circuit 35.

Bus control circuits 28, 29, 31, 33
Or line memories 22, 23 and addition 11: device 27
The timing of these operations is controlled by the address generation circuit 36, and the address generation circuit 36 is supplied with a lock signal or horizontal and vertical synchronization signals as necessary for timing control.

Here, the video signal converted into a digital signal by the single converter 8 is sent to the coefficient converter 5, but first, the bus control circuit 29 is closed and the video signal 23 is stored two lines before. is supplied to the addition circuit 32 in the adder 27. At this time.

The seven times the signal of the previous line stored in the line memory 22 is also supplied to the adding circuitry in the adder 27.

By adding the signal to the output of the adder circuit 32 latched by the latch circuit blade, a desired signal is obtained.

Addition in the adder 27 is started, and the line memo IJ
When the reading of the signals in 22 and 23 is completed, only the bus control circuit 29 is closed.

In this state, the signal multiplied by 1 by the coefficient unit U is stored in the line memory n.

Subsequently, only the bus control circuit 30 is closed, and the signal multiplied by 1 by the coefficient multiplier 25 is output.

It is stored in the line memory 22. Line memory 22゜n
The storage retention periods are one horizontal scanning period and two horizontal scanning periods, respectively, and these periods correspond to the delay time.

In this way, the digital filter 21 compresses the signals stored in the line memories 22 and 23 to 1 and 1, respectively, so the line memory 22 has a storage capacity of 1 bit, and the line memory n has a storage capacity of 2 bits. You can save money. Furthermore, since the coefficient multiplier 24 is shared for the current signal and the signal two lines before, the number of coefficient multipliers used can be reduced.

〔Effect of the invention〕

As explained above, according to the present invention, when forming a reduced image by thinning out horizontal scanning lines, before delaying the digital video signal related to the horizontal scanning line thinned out by one in the storage means, Since the structure is multiplied and weighted, there is no need to make all the storage means used have the same storage capacity, and the storage capacity can be reduced by the amount that the information is compressed as a result of 1 weighting. This allows for a simpler circuit configuration. This provides excellent effects such as being able to obtain a reduced image that has undergone vertical interpolation.

[Brief explanation of drawings]

1 and 2 are circuit configuration diagrams showing respective embodiments of the digital filter of the present invention, and FIG. 3 is a circuit diagram showing each embodiment of the digital filter of the present invention. FIG. 1 is a circuit configuration diagram showing an example of a conventional digital filter. 11, 21... digital filter, 12, 1
3, 22, 23... line memory, 14, 1
5, 16, 24, 25...Coefficient unit. 17, 27...adder.

Claims (1)

[Claims] a delay means for storing and delaying digital video signals related to horizontal scanning lines thinned out to obtain a reduced image for a time necessary for synchronization; A digital filter comprising a coefficient unit that multiplies the weighted average by a necessary coefficient.