JPS6127934B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a dynamic frequency divider circuit constituted by complementary connected insulated gate field effect transistors (hereinafter abbreviated as FETs).

As shown by the solid line in Figure 1, one inverter is connected immediately after an even number of inverters and transmission gates are connected in cascade, and the output of this inverter is fed back to the input terminal of the first stage inverter. It is well known that circuits are constructed. What is shown in the figure is a 1/6 frequency divider circuit. By using this method of controlling the on/off of the transmission gate using the two-phase clock signal φ, a stable dynamic frequency divider circuit that is unlikely to malfunction can be obtained. However, although the circuit shown by the solid line in FIG. 1 can divide the frequency by a factor of 1, it is impossible to divide the frequency by a factor of an odd number. The present invention aims to provide a method for configuring a frequency dividing circuit by an odd number while maintaining the above-mentioned stability. Furthermore, any 1/2n using the conventional construction method
(n = 1, 2, 3......) There is also a method of obtaining the desired 1/m frequency dividing circuit (where m is an integer such that 2≦m≦2n-1) by applying appropriate modification to the frequency dividing circuit. suggest.

First, as an example, a method for obtaining a 1/5 frequency divider circuit from a conventional 1/6 frequency divider circuit will be explained. The solid line in FIG. 1 is a conventional 1/6 frequency divider circuit constructed by alternately connecting six inverters and six transmission gates in cascade and further connecting one inverter. The transmission gate in the figure is a P channel FET,
It turns on when the clock signal entering the N-channel FET is low or high, and turns off when the opposite is true. The waveforms of the signals at the nodes A, B, C, D, E, F, and G of this frequency dividing circuit are as shown in FIG. 2, and it can be seen that frequency division is performed by 1/6. At this time, in FIG. 1, for example, there is an N channel as shown by a dotted line at node B.
Connect the drain 1 of FET 1 and input the signal of node A to the gate of FET 1. The source of FET1 is connected to the negative power supply V _SS . Due to the action of FET 1, the fall of the signal at node B occurs in synchronization with the rise of the signal at node A, as shown at timings T ₁ and T ₁₁ in FIG. At the same timing, since the transmission gate immediately before node C is turned on, the rise of the signal at node C also occurs at the same time. As a result, the operating waveform diagram at each node of the circuit in which FET 1 is added in FIG. 1 becomes as shown in FIG. 3, and it can be seen that 1/5 frequency division is performed.

Next, with FET 1 left in place, FET 2 is added to the node immediately after the next transmission gate, which receives the same phase clock signal as the transmission gate immediately before B, that is, node D, as shown in Figure 1. The signal at node A is input to that gate. FET1 and FET
Due to the function of 2, the timing in Figure 4
As shown in T ₁ T ₉ , the signal level is inverted not only at the nodes B and C described above but also at the node D. At this time, since the transmission gate immediately before node E is on, the signal rises at node E as well. As a result, the operating waveform diagram at each node of the circuit shown in FIG. 1 to which FET1 and FET2 are added becomes as shown in FIG. 4, where 1/4 frequency division is performed. Similarly, FET
The drain of P channel FET3 is connected to node B with FET1 and FET2 remaining, and the signal of node A is input to its gate. The source of FET3 is connected to the positive power supply _VDD . At this time, the operating waveform diagram at each node is as shown in FIG. 5, and 1/3 frequency division is performed. Furthermore, if FET 4 is added while leaving FETs 1, 2, and 3 in FIG. 1, the operating waveform diagram at each node becomes as shown in FIG. 6, and 1/2 frequency division is performed.

Above, examples have been described in which 1/5, 1/4, 1/3, and 1/2 frequency dividing circuits are obtained from a 1/6 frequency dividing circuit. In the present invention, in a conventional 1/2n frequency divider circuit, a signal at a node corresponding to the input end of a certain inverter is transferred to a FET added to a node corresponding to the output end of the first transmission gate counting from the inverter. By inputting to the gate of
A (2n-1) frequency divider circuit was realized. Furthermore, by sequentially adding FETs to the nodes immediately after the transmission gate, a desired 1/m frequency dividing circuit (m is 2≦m≦
2n-1 integers). In addition, in the frequency dividing circuit as shown in Fig. 1, Fig. 7a
The method proposed here can also be applied to a frequency dividing circuit obtained by replacing the basic cell shown in FIG. 7b with the basic cell shown in FIG.

[Brief explanation of the drawing]

In Figure 1, the solid line shows the 1/6 frequency divider circuit.
The N-channel FETs 1 and 2 and P-channel FETs 3 and 4 shown by the dotted lines are sequentially added to 1/5, 1/4,
It is a 1/3, 1/2 frequency divider circuit. In the figure, φ is a clock signal, φ is a clock signal opposite in phase to φ, V _SS is a negative power supply, and V _DD is a positive power supply. Figure 2, Figure 3, Figure 4
Figures 5, 6 are 1/6, 1/5, 1/4, respectively.
FIG. 3 is an operation waveform diagram of a 1/3 and 1/2 frequency divider circuit. Figure 7a
is the cascade connection of the transmission gate and the inverter, b is 2
This is a phase clock controlled inverter.

Claims (1)

[Scope of Claims] 1 (a) One stage consists of one complementary connection MOS inverter and one transmission gate, (b) 2n of said one stage are connected in cascade, (c) said 2n of In a dynamic frequency divider circuit in which the first stage and the final stage are ring-connected by one complementary connection MOS inverter, (d) an FET is inserted between the output terminal of the first stage and the power supply, and the FET is connected to the final stage. Said complementary connection
A dynamic frequency divider circuit characterized in that the output of the MOS inverter is connected to the gate of the FET to form a 1/(2n-1) frequency divider circuit.