JPS61292013A - Capacity type converter - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] <Industrial Application Field> The present invention relates to a capacitive transducer that converts physical displacement based on changes in physical quantities such as pressure and tension into electrical signals via capacitance. This invention relates to a capacitive conversion device with improved nonlinearity.

<Prior Art> Various types of capacitive transducers have been proposed that detect displacement and the like as changes in capacitance. For example, the details are disclosed in "Capacitive displacement converter" (Japanese Patent Laid-Open No. 57-26711) or the corresponding US Pat. No. 4,387,601.

The technology disclosed herein forms an oscillation circuit that alternately repeats charging through one of a pair of sensor capacitors and discharging through a bidirectional constant current circuit, and After the output frequency of the circuit is counted by a counter and reaches a certain number of counts, it is switched to the other sensor capacitance, and a first signal having a pulse width corresponding to the first sensor capacitance and the second sensor capacitance is generated. The pulse output of the second signal is obtained from the output end of the counter and is smoothed to obtain an output related to the ratio of the capacitance sum to the capacitance difference.

<Problems to be Solved by the Invention> However, in a capacitive conversion device having such a configuration, a common bias error in the capacitance conversion process causes the first signal,
This has the disadvantage that it adds to the capacitance sum and capacitance difference of the second signal and has an undesirable effect. More specifically, for example, the first signal and the second signal are time width signals T1 . When T2 is given, a common bias error Td is added to the first signal and the second signal due to the propagation delay characteristics of the internal logic element of the capacitance-time width converter, and as a result, the first signal and The second signals are T, +Td, and T2+Td, respectively, and the ratio of the capacitance sum to the capacitance difference is (T 1-72 )/(T 1 + T
2 + 2 Td), which applies a summative trap excitation to a pair of sensor capacitors in response to a force and applies an amount of electricity corresponding to the sum of the capacitances from each other end of the sensor capacitors to the input end. The device is configured to output a signal related to the ratio of the capacitance sum to the capacitance difference.

<Example> Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a circuit diagram showing a basic embodiment of the present invention.

CI and C2 are sensor capacitances that change depending on the physical quantity to be measured. One end of each of them is connected and connected to the input end of buffer gate G1.

A capacitor C3 having a fixed capacitance is connected between the input and output terminals of the buffer gate G1, and the voltage at its output terminal is positively fed back to the input terminal. The output terminal of the buffer gate G1 is also connected to the input terminal of the buffer gate G1 via an inverter G2 and a bidirectional constant current circuit CC.
3 constitutes a negative feedback circuit that discharges the charge positively fed back to the input terminal of the buffer gate G1 at a constant current value.

The above buffer gate G capacitor C3, inverter G2, and bidirectional constant current circuit CC constitute a self-excited oscillation circuit.

The output terminal of buffer gate G1 is the input terminal C of counter CT.
LK is connected. The n-bit output terminal Qn of the counter CT is connected to the input terminal of an integrator Q1, and its output terminal T.

A variable voltage V is obtained.

The output end Qn of the counter CT is connected to one end of the input of an AND gate G3 and one end of the input of an AND gate G5 via an inverter G. On the other hand, the output terminal of buffer gate G1 is connected to AND gate G3. G
5 are respectively connected to the other ends of the inputs. These AND gate G3. G5 and inverter GG constitute mode selector Q2.

The output terminal of the 4' 6 AND gate G is connected to the control terminals of the switches S and S to control the opening and closing of these. Apply positive power supply voltage +E to sensor capacitor C□ by making switch S1o,
By making the switch S11, a negative power supply voltage -E is applied to the resensor capacitor C2.

The switches S1o and S11 apply a differential voltage to the sensor capacitors CI and C2.

The output terminal of the AND gate G is connected to the control terminals of the switches S and S to control the opening and closing of these switches. Switch S1□, 3.
3 applies a variable pressure V to both sensor capacitors C1 and C2. A summation voltage is applied to the sensor capacitors C1 and C2 by the switches S12 and S13.

Moreover, the output terminal of the buffer gate G1 is connected to the switch S,
It is connected to the control end of S and controls the opening and closing of these. By making the switches S 1 and S 2 , a reference potential (zero potential) is applied to the other end of the sensing capacitor C11C2.

The above switches 518-815 are N-channel MO8F
It consists of ET and each switch is made by high-level logic, but other devices such as P-channel FET
It can be replaced with any switch such as %C-MOS.

The operation of the embodiment of FIG. 1 constructed as above will be explained using the waveform diagram shown in FIG. 2.

Buffer gate G1 has positive feedback to its power end via capacitor C3, inverter G2 and constant value constant current circuit CCK.
A negative feedback circuit and an unstable oscillation circuit are constructed, and a counter CT counts changes in the level of the output to the buffer gate.

When the counter CT counts a certain number, its output terminal Q
The level of n changes. When this level is 1H'' level, AND gate G5 is turned off, and AND gate G3 responds to the level change of the output of buffer gate G1 and outputs 1H'' level or -L level to its output terminal. Conversely, when the output terminal Qn of the counter CT is at the wL level, the AND gate G3 is turned off and the output level of the AND gate G5 changes according to the output level of the buffer gate G1. As described above, the mode selector Q2 selects the differential mode or the sum mode, which will be described later, depending on the level of the output of the counter CT.

Now, the output terminal Q of the counter CT is in a period T0 of 1 ■ level.
(Fig. 2 (c)) is assumed. In the state of period T, when the output terminal of the buffer gate G1 falls to the -E state (Fig. 2 (→), the bidirectional constant current circuit CCK discharges at a constant current value i in the opposite direction. 0), the potential at the input end of the buffer gate G1 continues to rise linearly, but when the threshold value vTHK of the buffer gate G is reached, the level at the output end is reversed and becomes +E. On the other hand, when the output level of the buffer Gl is -E, the output of the counter CT is wH level, so the output level of the buffer Gl is -E.
A potential at a level that is an inversion of the output level of the buffer gate G1 is applied to the switches S1o and S1 via G.
As shown in FIGS. 2(f) and (g), a potential of +E is applied to the sensor capacitor 01, and a potential of -E is applied to the sensor capacitor 02.

When the output of the buffer gate G□ is inverted as described above and becomes +E, the switch S10.1"11 is turned off and the switch U (second
Figure (f) (g)) Switch S14. S15 is turned on (as shown in FIG. 2(A)), and a reference potential (zero potential) is applied to the sensor capacitors C1 and C2.

Therefore, when the output level of the buffer gate G1 changes from -E to 10EK, the potential of the capacitor C3 changes by +2E (Fig. 2 (c)), and the potential of the sensor capacitor C changes by -E (
)), the sensor capacitance C2 is +E potential change (second
Figure (e)) is generated. Therefore, due to this potential change, the potential change e□ at the input end of the buffer gate G (Fig. 2 (a))
takes into account the total amount of charge transfer and becomes as shown in the following equation.

e (C+ C+C) = 2EC3-EC1+ EC
2 Therefore, .

After this, a linear discharge occurs from the bidirectional constant current circuit CCK, and when the threshold value vTH at the input terminal of the gate gate G is exceeded, its output is inverted, but the potential change e1' is e
It is the same value as l.

The above state is repeated for a period T1, and when a predetermined count is reached, the output of the counter CT is inverted to the I L level and held for a period T2.

In the state of period T, switches S, S and S are opened and closed by mode selector Q2 (as shown in FIG. 2), and switch S14"I is opened and closed by the output level of buffer gate G1.
s is opened and closed complementary to switches S1□ and S13 (
Figure 2 (!j)41)). In this case, the slope is sensor capacitance Cl
A variable voltage V is applied in common to -02 (see Fig. 2),
(to)) Therefore, taking this point into account, the same process as in the derivation of equation (1) is carried out, and the potential change e(=
e2') is calculated as follows.

On the other hand, the discharge time t1 for a potential change e1 and the discharge time t2 for a potential change e2 at a constant current i by the bidirectional constant current circuit CC are given by the following equations.

1, =(C1+02+03)e1/1(3)t2 =(
CI + C2+ 03) e2/i'
(4) Discharge time t1f for potential changes e' and e'
, t21 are given by the same values as in equations (3) and (4), respectively.

Here, using equations (1) and (2), (3) and (
4) Rewriting the equation, we get:

The integrator Q1 outputs a variable voltage V in response to the duty cycle value of the output pulse of the counter CT, and T□=T (z
"t = 2" t2) K naru! - Stop the variable ft pressure vid sono increase/decrease. The variable voltage V at this time (5),
(6) Formula % Formula % becomes. That is, it is obtained as a value proportional to the difference in the sum of the variable voltage V and the sensor capacitance.

In the embodiment shown in Fig. 1, the integrator Q was used to automatically adjust T I - T to 2, but the voltage ■ could be applied manually without relying on the integrator Q to make T1 = T2. It is also possible to obtain a value proportional to the difference in the sum of the sensor capacitances from the value of V at that time.

FIG. 3 shows a configuration in which the fixed capacitance C can also be erased when the fixed capacitance Cp is added to the sensor capacitances C1 and C2. This type of fixed capacitance C1 sensor is formed by a movable part and a terminal wiring part, and the smaller the sensor, the greater its influence becomes.

In this case, capacitors CA' and CB' are cA' =
(c1+c,')-(c2+cp)=C1-C2"'
CA (8)c Bt = (C
I + Cp)” (C2”Cp)12
p=CB+2Cp.

In FIG. 3, one end of a fixed capacitance capacitor C4 is connected to the input end of the buffer gate G0. Switches S16' and S17 are connected to the other end of the capacitor C4. Switch "16, like switch S10, is controlled by the output pressure of AND gate G3 and connects capacitor C4.
A variable voltage V is applied to the other end of the capacitor C4, and the switch S17, like the switch S14, is controlled by the output of the inverter G and applies a reference voltage (zero voltage) to the other end of the capacitor C4. A reference voltage is applied to the other end of the capacitor C4 during a period T2.

As can be seen from equations (8) and (9), the fixed capacitance C is eliminated in the differential mode, and enters as an error factor only in the summation mode, so the switch Open and close SS to apply variable voltage V to capacitor C4 (Figure 4 (b)).
, when the switches S and S are in the on-state sum mode, a reference potential is applied to the other end of the capacitor C4 (see Fig. 4).
b)), so the following equation holds true.

EC + VC = VCB + 2VCp (1G, where C
If 4=2C is selected, the fixed capacitance C at (g) 2 is eliminated, and the variable voltage V is obtained as a value proportional to the difference in the sum of the sensor capacitances.

FIG. 5 shows still another embodiment of the present invention, which differs from the case of FIG. 3 in that the supply of switch S19 in FIG. 5 is selected to be zero. One end of a fixed capacity capacitor C5 is connected to the input end of the buffer gate G. Switches S 1 and S 2 are connected to the other end of the capacitor C5. Switches S , S are switches S , S
However, the difference from FIG. 3 is that the supply of the switch S28 is changed from the variable voltage (2) to the negative power supply voltage -E. A switch S is also connected to the other end of the capacitor C5 and is opened and closed in synchronization with the switch "18."

In this embodiment, the supply of switch "19" is selected to be zero, so during differential mode excitation, the sensor capacitance C
2 is isometrically eliminated. Therefore, CA=C1-0・C2α CB=C1+02 (
Equilibrium of the electrical quantity is achieved in the relationship 6).

When a charge balance equation is derived in the same manner as equation 01 in FIG. 5, it becomes EC+VC-EC=VCB+2VCp-ECpcJ3.

Here, select C=2C,, C5=C, and C1 force,
(b) Obtain the formula % formula %. When formula 64 is modified, it becomes 1 +L; 2, and it is possible to obtain a variable voltage V that is proportional to the difference in the sum of sensor capacitances. In this case, the excitation waveform at the other end of the capacitor C5 is a waveform obtained by changing the peak value V of FIG. 4(G) by -EK.

FIG. 6 shows a fourth embodiment of the present invention, which is different from the supply of switch "15" in FIG. 1 in that the supply of switch S23 in FIG. 6 is changed by 10 EK. FIG. 7 shows changes in voltage waveforms at various parts in this case.

Comparing this waveform diagram with the waveform diagram shown in Figure 2, (1)
, it can be seen that the following change is given to the quantity of electricity of the sensor capacitor C2 in equation (2).

-EC2-21C2 VC2VC2-EC2 With this change, equations (1) and (2) become as follows.

(b) Using the α force equation and equations (3) and (4), t
When the equilibrium condition of 1 = t 2 is determined, the equation is the same as equation (7), and the variable voltage V is obtained as a value proportional to the difference in the sum of the sensor capacitances.

The above is a comparison between FIG. 1 and FIG. 6.

It can be seen that the supply voltage to the switches SIs and S23, which are operated in common during the differential mode period T1 and the summation mode period T2, may be any value.

The same applies to the case of switch "14. However, in the embodiment shown in FIG. 6 in which K + E is given, the third component related to the value of sensor capacitance C2 is Including K means that equations (3) and (4) become first-order equations (2) and C11.

tl = (2EC3-ECA+EC2)/i
(2) t = (2EC-VC+EC)/
'i 斡2 3 A 2 In addition, in the embodiment shown in Fig. 6, the characteristics are changed by adding a fixed capacitance, similar to the change from the embodiment shown in Fig. 1 to the embodiment shown in Fig. 3. be able to.

<Effects of the Invention> As described above in detail with the embodiments, according to the present invention, there is a configuration in which a signal is converted by providing a period for converting a capacitance difference between sensor capacitances into a signal and a period for converting a capacitance sum into a signal. Therefore, the calculation after signal conversion is simplified to a simple comparison calculation, and there is no need to calculate the sum and difference after signal conversion of the sensor capacitance as in the conventional case, and bias errors occurring in the signal conversion section can be removed. I can do it.

Furthermore, the differential mode and the sum mode are switched by the 1 mode select means, and a voltage is applied to the sum mode so that the periods of each mode are equal. From this voltage, the sum of the sensor capacitances can be calculated You can know the difference between

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing a first embodiment of the present invention, FIG. 2 is a waveform diagram showing waveforms of each part of the embodiment shown in FIG. 1, and FIG. 3 is a circuit diagram showing a second embodiment of the present invention. 4 is a ferry diagram showing the waveforms of each part of the embodiment shown in FIG. 3, FIG. 5 is a circuit diagram showing the third embodiment of the present invention, and FIG. 6 is a fourth embodiment of the present invention.
FIG. 7 is a waveform diagram showing waveforms of various parts of the embodiment of FIG. 6. G1...Buffer gate, G2. G4. G6...Inverter, Gs, Gs...And gate %CT...
Counter, ql...integrator, Q...mode selector" 10~s23...switch. % C1, C2...sensor capacitance, C2...fixed capacitance, ■...variable voltage, Ca , C41C5... Capacitor.

Claims (1)

[Claims] a pair of sensor capacitors that change in accordance with a physical quantity; a gate means to which each end of the sensor capacitors is connected and changes an output level in response to a change in input voltage exceeding a predetermined threshold; and an input end of the gate means. fixed capacitance means forming a positive feedback circuit to the fixed capacitance means, negative feedback means for discharging the input voltage generated by the positive feedback of the fixed capacitance means to return it to the threshold value, and controlling a change in the output level of the gate means to a predetermined value. a counting means for counting the number of times; a mode selection means for changing the excitation mode to the sensor capacitance according to the level of the output pulse of the counting means; and a pair of differential excitation means for differentially exciting the sensor capacitance and applying an amount of electricity corresponding to the capacitance difference from each other end of the sensor capacitance to the input end; and an output of the mode selection means and the integration means. and a summative excitation means for harmonically exciting the pair of sensor capacitors upon receiving the output, and applying an amount of electricity corresponding to the sum of the capacitances from each other end of the sensor capacitors to the input end, the capacitors A capacitive conversion device that outputs a signal related to the ratio of the sum and the capacitance difference.