JPS6130219Y2 - - Google Patents
Info
- Publication number
- JPS6130219Y2 JPS6130219Y2 JP1191681U JP1191681U JPS6130219Y2 JP S6130219 Y2 JPS6130219 Y2 JP S6130219Y2 JP 1191681 U JP1191681 U JP 1191681U JP 1191681 U JP1191681 U JP 1191681U JP S6130219 Y2 JPS6130219 Y2 JP S6130219Y2
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- installation stand
- lead wire
- semiconductor device
- probe
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 239000004065 semiconductor Substances 0.000 claims description 30
- 239000000523 sample Substances 0.000 claims description 19
- 238000009434 installation Methods 0.000 claims description 16
- WABPQHHGFIMREM-UHFFFAOYSA-N lead(0) Chemical compound [Pb] WABPQHHGFIMREM-UHFFFAOYSA-N 0.000 claims description 16
- 239000000758 substrate Substances 0.000 claims description 16
- 238000007689 inspection Methods 0.000 claims description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 2
- 229910052710 silicon Inorganic materials 0.000 claims description 2
- 239000010703 silicon Substances 0.000 claims description 2
- 238000010586 diagram Methods 0.000 description 3
- 239000002184 metal Substances 0.000 description 1
Landscapes
- Testing Of Individual Semiconductor Devices (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
Description
【考案の詳細な説明】
本考案は半導体装置の検査装置の改良に関する
ものである。シリコン(Si)基板上に形成した
IC,LSI等の半導体装置の電気的特性を自動的に
検査する半導体装置の検査装置は種々の形式があ
るが、ここで上記した検査装置の従来の構造につ
いて第1図を用いて説明する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an improvement in an inspection apparatus for semiconductor devices. formed on a silicon (Si) substrate
There are various types of semiconductor device testing devices that automatically test the electrical characteristics of semiconductor devices such as ICs and LSIs.Here, the conventional structure of the above-mentioned testing device will be explained with reference to FIG.
図は従来の特にMOS型の半導体装置の測定装
置の要部を概略的に示したもので図で示すように
回転可能な金メツキを施した金属表の円板形状の
基板設置台1上には半導体素子を形成したSi基板
2が載置されている。この設置台には別個に前記
半導体素子の被検査個所を測定し得るように所定
のパターンで配設された複数のプローブ3を内蔵
したプローブカード4が設けられ、該プローブカ
ード4に基板設置台が移動してはまり込むように
なり、前記プローブカードを前記半導体素子の所
定の箇処に接触させ、一方プローブカードより延
びるリード線5を基板設置台の裏面側より配置し
て前記設置台上に設置された基板の背面側の所定
箇処に接触させ、前記リード線に電圧に印加する
ことにより動作に必要な基板バイアスを与えた状
態で半導体装置の特性を検査するようになつてい
る。ところが前記半導体装置の所定の被検査箇処
を測定する場合、前記基板設置台1を回転させな
がら所定の被検査箇処を前記プローブに位置合せ
するようになつている。そのため前記プローブカ
ードより延びるリード線をあらかじめ基板設置台
が回転しても差し支えがないように余裕をもたせ
て長く形成してプリント板6の上に載せるように
している。 The figure schematically shows the main parts of a conventional measuring device, especially for MOS type semiconductor devices. A Si substrate 2 on which a semiconductor element is formed is mounted. A probe card 4 incorporating a plurality of probes 3 arranged in a predetermined pattern so as to be able to separately measure the test points of the semiconductor element is provided on this installation stand, and a substrate installation stand is installed on the probe card 4. moves and fits in, and the probe card is brought into contact with a predetermined location of the semiconductor element, while the lead wires 5 extending from the probe card are placed from the back side of the board installation stand and placed on the installation stand. The characteristics of the semiconductor device are tested while applying a substrate bias necessary for operation by contacting a predetermined location on the back side of the installed substrate and applying a voltage to the lead wire. However, when measuring a predetermined portion to be inspected of the semiconductor device, the predetermined portion to be inspected is aligned with the probe while rotating the substrate mounting table 1. For this reason, the lead wires extending from the probe card are formed in advance to be long enough to be placed on the printed board 6 so that there is no problem even when the board mounting table rotates.
しかしこのようにリード線を長くするとリード
線からノイズを拾つたりしてそのため正確に半導
体装置の特性が検査できないといつた欠点を生じ
ていた。 However, when the lead wires are made long in this way, noise is picked up from the lead wires, which makes it impossible to accurately test the characteristics of the semiconductor device.
本考案は前述した欠点を除去し、半導体装置に
電圧を印加するためのリード線の長さを短かくし
て該リード線よりノイズ等を拾つて測定される半
導体装置の検査情報が変動しないような高信頼度
の半導体装置の検査装置の提供を目的とするもの
である。 The present invention eliminates the above-mentioned drawbacks, shortens the length of the lead wire for applying voltage to the semiconductor device, picks up noise, etc. from the lead wire, and increases the temperature so that the test information of the semiconductor device measured does not fluctuate. The purpose of the present invention is to provide a reliable testing device for semiconductor devices.
かかる目的を達成するための半導体装置の検査
装置は半導体素子を形成したSi基板を設置する回
転可能な設置台と前記半導体素子の被検査箇処の
電気的特性を検査するプローブを有するプローブ
カードとよりなり、前記プローブカードより延び
るリード線を前記設置台に接続せしめ、前記リー
ド線に電圧を印加した状態で、前記プローブを基
板上の被検査箇処へ接触せしめて基板との半導体
素子の特性を検査する半導体装置の検査装置にお
いて、前記設置台の周辺部にプリント板を配設
し、該プリント板に端部が前記設置台の周辺部と
接触するような接触端子を有するリード線を設け
たことを特徴とするものである。 A semiconductor device testing apparatus for achieving this purpose includes a rotatable installation stand on which a Si substrate on which a semiconductor element is formed, and a probe card having a probe for testing the electrical characteristics of a portion of the semiconductor element to be tested. A lead wire extending from the probe card is connected to the installation stand, and with a voltage applied to the lead wire, the probe is brought into contact with a portion to be inspected on the board to determine the characteristics of the semiconductor element with the board. In a semiconductor device testing device for testing a semiconductor device, a printed board is disposed around the periphery of the installation stand, and a lead wire having a contact terminal whose end comes into contact with the periphery of the installation stand is provided on the printed board. It is characterized by:
以下図面を用いながら本考案の一実施例につき
詳細に説明する。 An embodiment of the present invention will be described in detail below with reference to the drawings.
第2図は本考案に係る半導体装置の検査装置の
要部の概略図である。 FIG. 2 is a schematic diagram of the main parts of the semiconductor device inspection apparatus according to the present invention.
図示するように本考案の半導体装置の測定装置
は基板設置台1の周辺部にプリント基板11が設
けられ、前記プリント基板上にはプローブカード
より延び半導体素子を形成しているSi基板の背面
より電圧を印加するためのリード線5より延びる
配線が中継点12で分岐されてリード線13A,
13B,13C,となり該リード線13A,13
B,13C,の先端部にはリレーの接点のような
銀メツキを施した弾力性のある薄い金属板の接点
14に接続されている。そして前記接点は基板設
置台1が回転する際に該設置台の周辺部を摩擦し
ながら接触するようになつている。ここで図では
リード線5を中継点12で3方向に分岐して接点
14を3つ設けてあるが、これは仮に1個または
2個の接点が摩耗しても他の接点によつてリード
線5と基板設置台1との接続が充分とられるよう
になつている。 As shown in the figure, in the semiconductor device measuring device of the present invention, a printed circuit board 11 is provided around the periphery of a substrate mounting table 1, and the printed circuit board 11 extends from the probe card and extends from the back side of the Si substrate forming the semiconductor element. Wiring extending from the lead wire 5 for applying a voltage is branched at the relay point 12 to form lead wires 13A,
13B, 13C, and the lead wires 13A, 13
The tips of B and 13C are connected to a contact 14 made of a silver-plated thin elastic metal plate like a relay contact. The contact points are adapted to come into contact with the periphery of the substrate installation table 1 while rubbing against it when the substrate installation table 1 rotates. Here, in the figure, the lead wire 5 is branched into three directions at the relay point 12, and three contacts 14 are provided, but this means that even if one or two contacts wear out, the lead wire 5 can be redirected by other contacts. The wire 5 and the board mounting stand 1 are sufficiently connected.
以上述べたように本考案の半導体装置の検査装
置によればプローブカードより延びて基板設置台
に接触するリード線の長さが従来の装置と比較し
て短かくなり、したがつてリード線よりノイズを
拾うようなことも少なくなり、検査精度のよい高
信頼度の半導体装置の検査装置が得られる利点を
生じる。 As described above, according to the semiconductor device inspection device of the present invention, the length of the lead wire that extends from the probe card and contacts the board installation stand is shorter than that of the conventional device, and therefore the lead wire is shorter than the lead wire. There is also less noise picked up, resulting in the advantage that a highly reliable semiconductor device testing device with good testing accuracy can be obtained.
第1図は従来の半導体装置の検査装置の要部概
略図を示し第2図は本考案による検査装置の要部
概略図を示す。
1:基板設置台、2:Si基板、3:プローブ、
4:プローブカード、5:リード線、6,11:
プリント基板、12:中継点、13A,13B,
13C:リード線、14:接触端子。
FIG. 1 is a schematic diagram of the main parts of a conventional semiconductor device testing apparatus, and FIG. 2 is a schematic diagram of the main parts of a testing apparatus according to the present invention. 1: Substrate installation stand, 2: Si substrate, 3: Probe,
4: Probe card, 5: Lead wire, 6, 11:
Printed circuit board, 12: Relay point, 13A, 13B,
13C: Lead wire, 14: Contact terminal.
Claims (1)
置する回転可能な設置台と、前記半導体素子の被
検査箇処の電気的特性を検査するプローブを有す
るプローブカードとからなり、前記プローブカー
ドより延びるリード線を前記設置台に接続せし
め、前記リード線に電圧を印加した状態で前記プ
ローブを基板上の被検査箇処へ接触せしめて基板
上の半導体素子の特性を検査する半導体装置の検
査装置において、前記設置台の周辺部にプリント
板を配設し該プリント板に端部が前記設置台の周
辺部と接触するような接触端子を有するリード線
を設けたことを特徴とする半導体装置の検査装
置。 It consists of a rotatable installation stand on which a silicon (Si) substrate on which a semiconductor element is formed, and a probe card having a probe for testing the electrical characteristics of a portion to be tested of the semiconductor element, and a lead extending from the probe card. In a semiconductor device testing apparatus that tests the characteristics of a semiconductor element on a substrate by connecting a wire to the installation stand and bringing the probe into contact with a portion to be inspected on the substrate with a voltage applied to the lead wire, An inspection device for a semiconductor device, characterized in that a printed board is disposed around the periphery of the installation stand, and a lead wire having a contact terminal whose end comes into contact with the periphery of the installation stand is provided on the printed board. .
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1191681U JPS6130219Y2 (en) | 1981-01-30 | 1981-01-30 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1191681U JPS6130219Y2 (en) | 1981-01-30 | 1981-01-30 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS57126085U JPS57126085U (en) | 1982-08-06 |
| JPS6130219Y2 true JPS6130219Y2 (en) | 1986-09-04 |
Family
ID=29810040
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1191681U Expired JPS6130219Y2 (en) | 1981-01-30 | 1981-01-30 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6130219Y2 (en) |
-
1981
- 1981-01-30 JP JP1191681U patent/JPS6130219Y2/ja not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| JPS57126085U (en) | 1982-08-06 |
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