JPS6130253U - 半導体装置 - Google Patents

半導体装置

Info

Publication number
JPS6130253U
JPS6130253U JP1984114643U JP11464384U JPS6130253U JP S6130253 U JPS6130253 U JP S6130253U JP 1984114643 U JP1984114643 U JP 1984114643U JP 11464384 U JP11464384 U JP 11464384U JP S6130253 U JPS6130253 U JP S6130253U
Authority
JP
Japan
Prior art keywords
semiconductor element
heat sink
semiconductor equipment
darlington transistor
stage portion
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1984114643U
Other languages
English (en)
Inventor
龍夫 松浦
Original Assignee
関西日本電気株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 関西日本電気株式会社 filed Critical 関西日本電気株式会社
Priority to JP1984114643U priority Critical patent/JPS6130253U/ja
Publication of JPS6130253U publication Critical patent/JPS6130253U/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/851—Dispositions of multiple connectors or interconnections
    • H10W72/874—On different surfaces
    • H10W72/884—Die-attach connectors and bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/921—Structures or relative sizes of bond pads
    • H10W72/926—Multiple bond pads having different sizes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/931—Shapes of bond pads
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/736—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked lead frame, conducting package substrate or heat sink
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/756—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked lead frame, conducting package substrate or heat sink

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。

Description

【図面の簡単な説明】
第１図は本考案に係るダーリントントランジスタの一実
施例の素子パターンの平面図で、第２図はそのＢ−Ｂ線
断面図、第３図は本考案に係るダーリントントランジス
タの他の実施例の断面図、第４図は本考案に係るダーリ
ントントランジスタの素子表面の温度分布図、第５図は
樹脂封止型半導体装置の要部断面図、第６図はダーリン
トントランジスタの回路図、第７図はダーリントントラ
ンジスタの素子パターンの平面図で、第８図はそのＡ−
Ａ線断面図、第９図は従来のダーリントントランジスタ
の素子表面の温度分布図である。 ２・・・半導体素子、３・・・半田部材、４・・・リー
ド部、５・・・金属細線、６・・・樹脂材、７，８・・
・放熱板、７ａ・・・放熱板の突起、８ａ・・・放熱板
の凹部、Ｔｒ１・・・ドライバー段、Ｔｒ２・一・パワ
ー段。

Claims (1)

    【実用新案登録請求の範囲】
  1. 放熱板に半導体素子を半田部材を使って固定すると共に
    リード部と半導体素子の電極とを電気的に接続し、半導
    体素子を含む主要部を樹脂材にて被覆したものにおいて
    、半導体素子をダーリントントランジスタとし、そのパ
    ワー段部分に対応する放熱板上面と半導体素子下面との
    間の半田厚を、ドライバー段部分に対応する放熱板上面
    と半導体素子下面との間の半田厚よりも薄くしたことを
    特徴とする半導体装置。
JP1984114643U 1984-07-26 1984-07-26 半導体装置 Pending JPS6130253U (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1984114643U JPS6130253U (ja) 1984-07-26 1984-07-26 半導体装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1984114643U JPS6130253U (ja) 1984-07-26 1984-07-26 半導体装置

Publications (1)

Publication Number Publication Date
JPS6130253U true JPS6130253U (ja) 1986-02-24

Family

ID=30673655

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1984114643U Pending JPS6130253U (ja) 1984-07-26 1984-07-26 半導体装置

Country Status (1)

Country Link
JP (1) JPS6130253U (ja)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS507338B1 (ja) * 1970-12-29 1975-03-25

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS507338B1 (ja) * 1970-12-29 1975-03-25

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