JPS613455A - Method of producing field effect transistor - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an improved method for manufacturing field effect transistors.

As is generally known, in many circuit applications it is desirable that the source-drain junction capacitance and series resistance between the channel and source-drain contacts of a field effect transistor be as small as possible. Junction capacitance can be reduced by reducing the area of the source and drain regions. However, this creates problems in aligning these areas and contacts. Shallowing the depth of the source and drain junctions increases the series resistance between the source and drain contacts and the channel. This resistance can be reduced by placing the contacts close to the channel region. This again creates problems as to the correct alignment of the contacts with respect to the channels.

Accordingly, there is a need to provide a method of manufacturing a field effect transistor that improves the alignment of the W contacts with various regions of the field effect transistor in a practical and reproducible manner.

i1 Yutaka IJ The method of the present invention consists of creating a patterned multilevel structure that includes successive layers of gate electrode metal, first insulator, and silicide-forming metal over the channel region of the device. A second insulator is formed along the edges of the multilevel structure. A layer of polycrystalline silicon is disposed over approximately the entire transistor area and a silicide-forming metal is reacted with the polycrystalline silicon to form a metal silicide. The metal silicide is then selectively etched without affecting the first or second insulator or the remaining polycrystalline silicon layer.

As shown in Figure 1, the processing method starts with a silicon substrate 10, which in this example is of the P-type conductivity type, on which an insulating layer 11 of SiO2 is deposited as standard. A thin layer 13 (typically referred to as the gate oxide) is formed over the semiconductor area that is to become the transistor and to mask the area outside the transistor and provide electrical isolation. It consists of a thick section 12 (field oxide) which serves to provide a field oxide.

As illustrated in FIGS. 2 and 3, a multilevel strip-like (FIG. 3) structure is formed over the area of the semiconductor and adjacent portions of field oxide layer 12 that will become the channel walls of the transistor. Formed by standard vapor deposition and photolithography. The structure consists of a gate electrode metal 14 of e.g. polycrystalline silicon, an insulating layer 15 of e.g. For example, it may consist of a composite layer of Ta5iz silicide. Formed on the metal layer 16 is another insulating layer 17 of, for example, SiO□ or 513N4, which is desirable to protect the metal 16 from subsequent processing, with a typical thickness of 4000K for the layer 14, a layer of 2000x for layer 15, 2000x for layer 16 and 2000x for layer 17. The layered structures 14-17 in this example are about 1 gm laterally and about 1 μm tall in FIG.

The next processing step is chosen to provide an insulating layer 18 (FIG. 4) on the edges of the layered structure to offset the final gate structure from later formed contacts. Several methods are available to form this offset insulator. In this example, a layer of 5i02 (FIGS. 2 and 3) is deposited over the entire structure to a thickness of approximately 1000 μm.

The workpiece is then treated with known reactive ion etching techniques to anisotropically etch all of the SiO□ material exposed to the ion beam. As is known, the method is anisotropic and etches only planes perpendicular to the ion beam, but not parallel planes, i.e. horizontally extending parts of layers 11, 17 and 18. are etched, but the vertically extending portions of layers 17 and 18 are not etched. Etching continues until layer 16 is exposed.

The results are as shown in FIGS. 4 and 5.

The horizontally extending portions of layers 17 and 18 have been removed. Thin oxide layer 13 has been removed to expose the surface of substrate IO. The layer remains due to its great thickness under Calendar 12. Similarly, the vertically extending portions of calendars 17 and 18 remain along the side walls of the calendared structures 14-16.

Since the oxide layer 8 remains on the side wall of the corner 12, the opening width height (Fig. 1) is slightly reduced.If both the 0 layers 12 and 18 are made of the same material, for example 5i02, For reasons of convenience, the additional layer 18 on the sidewalls of layer 12 is not shown in FIG. 1 layer 17 is removed as part of the reactive ion etching process. If layer 17
If it is made of a material other than 5i02, for example S+3N, it is removed in a separate wet etching process.

As shown in FIG. 6, a doped polycrystalline silicon layer 9 is then formed over substantially the entire structure.

The layer can be doped in situ during chemical vapor deposition or by subsequent implantation of dopants. In this example, the layer is arsenic (A
s) and deposited by standard chemical vapor deposition at a temperature of about 600'C to a thickness of about 2000λ. In processing, the exposed Pd layer 16 of structures 14-16 reacts with the polycrystalline silicon to form a PdSi layer, 20.

This silicide layer is then applied to the remainder of the polycrystalline silicon layer 19 or the SiO layer 1, as illustrated in FIG.
It is selectively etched without etching 5 and 18. For example, Eva 12g IIIi, 50 m1
H20,8gmKr so, 725+wl KOH (1/-
(7) Can be achieved with a mixture of different etching solutions. In the device after processing, the separate individual portions of layer 19 serve as contacts to the source and drain regions of the transistor. The above-mentioned advantage is that the contacts are automatically correctly positioned with respect to different areas of the device (self-alignment). Also, the possibility of source-gate-drain shorts is significantly reduced.

As shown in FIG. 8, As from polysilicon 19 is then diffused into the exposed underlying semiconductor region to form source and drain regions 21 and 22, respectively. A typical heating step is performed at 950° C. for about 30 minutes. The field oxide shields the semiconductor substrate 10 outside the transistor area from diffusion. The final junction depth of the source and drain regions is set after all subsequent heat treatments.

Polycrystalline silicon layer 19 is then patterned by standard photolithography as illustrated in the top view of FIG. The final pattern of polycrystalline silicon layer extends over the field oxide portions adjacent to the source and drain regions, and also seals the source and drain regions from contamination. Polycrystalline silicon layer 19 is then converted to a silicide layer (26 in Figure 1O) by depositing a metal such as cobalt and heating. Typical heating steps are 450°C for 30 minutes in H and 900°C for 30 minutes in 2% zero. The polycrystalline layer has the same shape as the polycrystalline layer. If desired, a silicide layer can be formed before patterning the metal.

The use of silicide layer 26 reduces the series resistance between the contacts to the source and drain regions and the channel. That's layer 26
is formed upright with respect to gate oxide 13 and as close as possible to the edges of the channel. Although in this example the entire polysilicon layer has been converted to silicide, it is also possible to change only the thicker portions of the layer and leave multiple layers of polysilicon-silicide. In either case,
The vertical dimensions of the source and drain regions are
No shrinkage occurs due to the conversion of the surface area to silicide. Such contraction, if it occurs, increases the series resistance of the device.

Furthermore, the series resistance between the source and drain and the channel can be optimized by controlling the relative thicknesses of the polysilicon and silicide layers without the need to increase the source and drain junction depths.

At the end of the process, as shown in FIG. 10, the device is covered with layer 23, such as phosphorous-doped glass, and windows 32 and 33 are opened therein by standard photolithography to partially remove layer 26. to be exposed to. The contacts are made of contact metal 24 and 2 such as aluminum at the window.
5 through the silicide layer 26 for the source and drain. Ohmic contacts are made on the field oxide rather than directly on the source and drain regions. This offers several advantages. First, the source and drain silicide contact areas 30 and 31 can be made small (preferably less than 0.5 pLm) because the aluminum contact windows 32 and 33 do not need to be aligned therewith. Second, it eliminates the problem of spikes between aluminum and silicon substrates. Furthermore, since the contacts 24 and 25 to the source and drain are approximately at the same height as the contacts to the gate electrode (not shown),
Makes etching easier. This eliminates the wind growth (or blooming) problem.

This problem causes the windows to gate electrodes that are exposed to overetching while the windows for the source and drain continue to be etched. The required overlap of layers 26 around the window is unnecessary.

This is because even if there is misalignment, overetching is rarely required when all window depths are the same. Although metal contacts 24 and 25 are shown overlapping contact windows 32 and 33, this overlap is not necessary. The layout area is thereby reduced. Ultimately, forming contacts on the field oxide reduces the depth of windows 32 and 33 and therefore improves the coverage of the aluminum metal process.

Several variations of the invention are possible. For example, although an enhanced mode device is illustrated, the invention is applicable to all types of field effect transistors. Self-aligned removal of the polysilicon on the gate is achieved in the example described above by initially patterning the multi-level structure, but other methods may also be employed. For example, a polysilicon gate is defined by standard methods and, following sidewall oxide formation, silicide-forming metal is selectively plated or deposited by chemical vapor deposition onto the gate electrode. polysilicon layer 19
is then deposited and a silicide is created as described above. Therefore, formation of multi-level structures containing silicide-forming metals is not required prior to processing. Silicide-forming metals that can be used in addition to palladium include nickel, tungsten and tantalum.

[Brief explanation of drawings]

1 to 10 are diagrams showing a field effect transistor at each step of the manufacturing method according to an embodiment of the present invention. Figures 1, 2, 4, 6, 7, 8 and 10 show the successive steps of the method, and Figures 3 and 5 represent the third
9 is a top view of FIG. 8; FIG. 9 is a top view of FIG. 8; Explanation of symbols of main parts> Gate electrode metal ・・・・・・・・・ 14 No. 1
Insulator ・・・・・・・・・ 15 Silicide-forming metal ・・・・・・・・・ 16 Second insulator ・・・・・・・・・ 18 Metal silicide
・・・・・・・・・ 20 polycrystalline silicon layers
...18 Applicant American Telephone & Telegraph Cambunny Procedural Amendment 1 U.S.C. July 11, 1959

Claims (1)

[Claims] 1. A method for manufacturing a field effect transistor including a source and drain region formed on the surface of a semiconductor substrate and a channel region between them; a first gate electrode metal (14) on the channel region; Forming a multi-level structure consisting of successive layers of an insulator (15) and a silicide-forming metal (16), with a second insulator (18) along the edges of the layered structure.
), depositing a layer (19) of polycrystalline silicon over substantially the entire transistor area and depositing the silicide-forming metal (16).
reacting with polycrystalline silicon to form a metal silicide (20) on the layered structure, and forming the metal silicide without affecting the first or second insulator or the remaining polycrystalline silicon layer. A method for manufacturing a field effect transistor characterized by selective etching. 2. A method as claimed in claim 1; converting at least part of the thickness of the remaining polycrystalline silicon layer (19) into a second silicide layer (26) and on a part of the layer. A method for manufacturing a field effect transistor, characterized in that an ohmic contact is created there by forming contact metals (24, 25) there. 3. The method according to claim 2, wherein the polycrystalline silicon layer (19) is formed on a third insulating layer (11) comprising a thick part and a thin part and an ohmic contact is formed on the source ( 21) A method for manufacturing a field effect transistor, characterized in that it is made for a silicide layer on a thick part of the insulator in the region removed from the drain (22) region. 4. A method for manufacturing a field effect transistor according to claim 3, characterized in that the polycrystalline silicon layer is only partially converted into silicide. 5. The method according to claim 1, wherein the gate electrode metal (14) is made of polycrystalline silicon, the first insulator (15) is made of silicon dioxide, and the silicide-forming metal (16) is made of polycrystalline silicon. ) is a method for manufacturing a field effect transistor characterized by being made of palladium. 6. A method for manufacturing a field effect transistor according to claim 3, characterized in that the ohmic contact is made of a metal consisting of aluminum to the silicide layer (26). 7. In the method according to claim 3, the second silicide layer has an opening (
30, 31) A method for manufacturing a field effect transistor, characterized in that a contact is made to the source and drain through the wire. 8. The method of claim 1, wherein the second insulator (18) is layered by depositing a silicon dioxide layer on the transistor and anisotropically etching the layer. A method for manufacturing a field effect transistor characterized in that it is formed along the side edges of a structure. 9. A method according to claim 1, characterized in that the polycrystalline silicon layer (19) contains impurities which are diffused into the semiconductor to form source and drain regions. Manufacturing method.