JPS614237U - video tape recorder - Google Patents
video tape recorderInfo
- Publication number
- JPS614237U JPS614237U JP8432884U JP8432884U JPS614237U JP S614237 U JPS614237 U JP S614237U JP 8432884 U JP8432884 U JP 8432884U JP 8432884 U JP8432884 U JP 8432884U JP S614237 U JPS614237 U JP S614237U
- Authority
- JP
- Japan
- Prior art keywords
- tape recorder
- video tape
- circuit element
- signal
- selector circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000015654 memory Effects 0.000 claims description 4
- 230000001360 synchronised effect Effects 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 2
Landscapes
- Information Transfer Systems (AREA)
- Multi Processors (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図は本考案の実施例のブロック図、第２図は第１図
の信号のタイミング関係を示す図である。
１，２：中央処理装置、１−１．２−１：割込信号入力
端子、１−２．２−２：信号バスライン、３，４：入出
力パスセレクタゲート、３一１．４−１：制御端子、３
−２．３−３．４−２．４−３：入出力バス端子、５：
メモリ（ＲＡＭ）、６：制御信号発生器、７：ｃｐｕ１
，２の入出力バス、８：メモリ入出力バス、９，１０；
制御信号、１１：垂直同期信号。FIG. 1 is a block diagram of an embodiment of the present invention, and FIG. 2 is a diagram showing the timing relationship of the signals in FIG. 1. 1, 2: Central processing unit, 1-1.2-1: Interrupt signal input terminal, 1-2.2-2: Signal bus line, 3, 4: Input/output path selector gate, 3-1.4- 1: Control terminal, 3
-2.3-3.4-2.4-3: Input/output bus terminal, 5:
Memory (RAM), 6: Control signal generator, 7: CPU1
, 2 input/output bus, 8: memory input/output bus, 9, 10;
Control signal, 11: Vertical synchronization signal.
Claims (1)
するビデオテープレコーダにおいて、１個又は複数個の
メモリを有し、このメモリの入出力信号と制御信号バス
と各々のＣＰＵの入出力信号と制御信号バスとの間を双
方向、片方向のトライステート又はオープンコレクタ出
力等のセレグタ回路素子を用いて接続し、セレクタ回路
素子の制御をビデオ信号に含まれる同期信号又はビデオ
信号に同期した信号によって作られた制御信号で行うよ
うにしたビデオテープレコーダ。A video tape recorder having a plurality of digital computers (hereinafter referred to as CPUs) has one or more memories, and input/output signals and control signal buses of the memory and input/output signals and control signal buses of each CPU. A selector circuit element such as bi-directional, unidirectional tri-state or open collector output is used to control the selector circuit element, and the selector circuit element is controlled by a synchronization signal included in the video signal or a signal synchronized with the video signal. A video tape recorder that operates using controlled signals.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8432884U JPS614237U (en) | 1984-06-08 | 1984-06-08 | video tape recorder |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8432884U JPS614237U (en) | 1984-06-08 | 1984-06-08 | video tape recorder |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS614237U true JPS614237U (en) | 1986-01-11 |
Family
ID=30633752
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP8432884U Pending JPS614237U (en) | 1984-06-08 | 1984-06-08 | video tape recorder |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS614237U (en) |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5394745A (en) * | 1977-01-31 | 1978-08-19 | Copal Co Ltd | Method of processing data |
| JPS57152057A (en) * | 1981-03-14 | 1982-09-20 | Toshiba Corp | Memory device |
-
1984
- 1984-06-08 JP JP8432884U patent/JPS614237U/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5394745A (en) * | 1977-01-31 | 1978-08-19 | Copal Co Ltd | Method of processing data |
| JPS57152057A (en) * | 1981-03-14 | 1982-09-20 | Toshiba Corp | Memory device |
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